greg_counters: move rx_pause event outside rx status reg insert block

modules/wr_endpoint/ep_rx_path.vhd

@@ -300,6 +300,7 @@ architecture behavioral of ep_rx_path is
   signal ematch_done     : std_logic;
   signal ematch_is_hp    : std_logic;
   signal ematch_is_pause : std_logic;
+  signal fc_pause_p      : std_logic;
 
   signal pfilter_pclass : std_logic_vector(7 downto 0);
   signal pfilter_drop   : std_logic;
@@ -319,6 +320,9 @@ begin  -- behavioral
 
   fab_pipe(0) <= pcs_fab_i;
 
+  fc_pause_p_o    <= fc_pause_p;
+  rmon_o.rx_pause <= fc_pause_p;
+
   U_early_addr_match : ep_rx_early_address_match
 
     port map (
@@ -333,7 +337,7 @@ begin  -- behavioral
       match_is_pause_o        => ematch_is_pause,
       match_pause_quanta_o    => fc_pause_quanta_o,
       match_pause_prio_mask_o => fc_pause_prio_mask_o,
-      match_pause_p_o         => fc_pause_p_o,
+      match_pause_p_o         => fc_pause_p,
       regs_i                  => regs_i);
 
   gen_with_packet_filter : if(g_with_dpi_classifier) generate

modules/wr_endpoint/ep_rx_status_reg_insert.vhd

@@ -75,7 +75,6 @@ begin  -- rtl
             
           when WAIT_MBUF =>
             if(mbuf_valid_i = '1') then
-                rmon_o.rx_pause        <= mbuf_is_pause_i;
                 rmon_o.rx_pfilter_drop <= mbuf_drop_i;
 
                 if(mbuf_drop_i = '0' and mbuf_is_pause_i = '0') then
@@ -92,7 +91,6 @@ begin  -- rtl
                 sreg.error       <= '0';
             else
               rmon_o.rx_pfilter_drop        <= '0';
-              rmon_o.rx_pause               <= '0';
               rmon_o.rx_path_timing_failure <= '0';
             end if;