virtex6 use phy from wr-switch-sw-v7.0

platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd

@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-11-18
--- Last update: 2023-12-11
+-- Last update: 2013-12-20
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -39,7 +39,6 @@
 -- 2010-11-18  0.4      twlostow  Ported EASE design to VHDL 
 -- 2011-02-07  0.5      twlostow  Verified on Spartan6 GTP
 -- 2011-09-12  0.6      twlostow  Virtex6 port
--- 2023-12-11  0.7      peterj    Artix7 gtp depends on rx_byte_is_aligned
 -------------------------------------------------------------------------------
 
 library ieee;
@@ -50,9 +49,8 @@ entity gtp_bitslide is
   
   generic (
 -- set to non-zero value to enable some simulation speedups (reduce delays)
-    g_simulation             : integer;
-    g_target                 : string  := "spartan6";
-    g_use_rx_byte_is_aligned : boolean := false);
+    g_simulation : integer;
+    g_target     : string := "spartan6");
 
   port (
     gtp_rst_i : in std_logic;
@@ -89,16 +87,6 @@ end gtp_bitslide;
 architecture behavioral of gtp_bitslide is
 
 
-  function f_eval_link_down_threshold return integer is
-  begin
-    if(g_simulation /= 0) then
-      return 256;
-    else
-      return 10000; -- 10000 bytes without comma = link down
-    end if;
-  end f_eval_link_down_threshold;
-  
-  
 
   function f_eval_sync_detect_threshold
     return integer is
@@ -213,15 +201,7 @@ begin  -- behavioral
 
         when S_PAUSE =>
           counter        <= counter + 1;
-          if g_target = "ultrascale" then
-            if counter = 1 then
-              gtp_rx_slide_o <= '0'; -- ultrascale requires 2 RXUSRCLK2 ticks
-                                     -- for slide pulse
-            end if;
-          else
-            gtp_rx_slide_o <= '0';
-          end if;
-            
+          gtp_rx_slide_o <= '0';
 
           if(counter = to_unsigned(c_pause_tics, counter'length)) then
 
@@ -229,7 +209,6 @@ begin  -- behavioral
               state <= S_SLIDE;
             else
               state <= S_GOT_SYNC;
-              counter <= to_unsigned(0, counter'length);
             end if;
           end if;
 
@@ -237,21 +216,10 @@ begin  -- behavioral
           gtp_rx_slide_o <= '0';
           bitslide_o     <= std_logic_vector(cur_slide(4 downto 0));
           synced_o       <= '1';
-          if gtp_rx_comma_det_i = '1' then
-            counter <= to_unsigned(0, counter'length);
-          else
-            counter <= counter + 1;
-          end if;
-
-          if(g_use_rx_byte_is_aligned = true and (gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0')) then
-            gtp_rx_cdr_rst_o <= '1';
-            state            <= S_SYNC_LOST;
-          elsif (g_use_rx_byte_is_aligned = false and counter = f_eval_link_down_threshold) then
-            report "serdes: link down" severity error;
+          if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
             gtp_rx_cdr_rst_o <= '1';
             state            <= S_SYNC_LOST;
           end if;
-
         when others => null;
       end case;
     end if;

platform/xilinx/wr_gtp_phy/virtex6/wr_gtx_phy_virtex6.vhd

@@ -201,8 +201,7 @@ architecture rtl of wr_gtx_phy_virtex6 is
   component gtp_bitslide
     generic (
       g_simulation : integer;
-      g_target     : string := "virtex6";
-      g_use_rx_byte_is_aligned : boolean := false);
+      g_target     : string := "virtex6");
     port (
       gtp_rst_i                : in  std_logic;
       gtp_rx_clk_i             : in  std_logic;
@@ -389,8 +388,7 @@ begin  -- rtl
   U_Bitslide : gtp_bitslide
     generic map (
       g_simulation => g_simulation,
-      g_target     => "virtex6",
-      g_use_rx_byte_is_aligned => true)
+      g_target     => "virtex6")
     port map (
       gtp_rst_i                => gtx_rst,
       gtp_rx_clk_i             => rx_rec_clk,