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Wrreferencedesign

Last edited by Erik van der Bij
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White Rabbit Node Reference Design

The White Rabbit PTP Core (WRPC) is an HDL module that could be easily synthesized and used as a standalone WR interface inside a single FPGA chip or as an IP core in a larger design. WRPC was created to simplify the integration of WR into both existing and embedded devices and systems. This wiki page briefly describes the requirements to upgrade an existing system and has links to some compact standalone solutions.

WRPC implements an IEEE1588 ordinary clock capable of reaching sub-nanosecond accuracies and working in GrandMaster, Master or Slave mode:

  • GrandMaster: WR Master synchronized to an external 1-PPS and 10 MHz clock signal, propagates precise timing to other WR-compliant devices
  • Master: WR Master with free-running oscillator, propagates precise timing to other WR-compliant devices
  • Slave: Synchronizes its internal oscillator to another WR Master device and provides the timing information for other IP cores through a simple VHDL interface

The drawing below depicts the internal modules of WRPC:

Detailed description see:

Upgrade an existing system

Only a few additional components are required to upgrade an existing system with WRPC, presuming the existing system already includes an appropriate FPGA and the required environmental hardware (power supply, configuration etc.). WRPC has been successfully tested with GTP and GTX transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family), support for Altera GX PHYs is currently being implemented.

Block Diagram

Required components:

  • SFP module (fiber optic transceiver)
  • Two digitally tunable clock generators
    • one for the main PLL
    • one for producing the DMTD offset frequency

Optional components:

  • EEPROM (I2C interface) to store configuration data
  • Unique ID / Temperature sensor (one-wire interface) to build the MAC address
  • I/O connector with user I/O signals

The total cost of the external components, including the SFP module is around 75 Euros.
A part of the price of the Xilinx (search price) resources could be added.

Operating Power

  • FPGA: ~ 1 W
  • Clock generators: ~ 700 mW
  • FO Transceiver: ~ 500 mW

FPGA Utilization Summary

The table below shows the FPGA utilization summary of the WRPC relevant resources only (WRPC v2.1, Spartan-6, XC6SLX45T-3FGG484, ISE 13.4):

More information:

Compact standalone solutions

Some projects which are standalone White Rabbit Node implementations:

Contacts

Useful references

Daniel Florin - 7 May 2021

Files