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# Frequently Asked Questions
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Q: Does the core support RORA mode (Release on Register Access)?
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The core does not support the RORA mode.
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-----
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## General
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### Q: what is really the state of the design?
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State in March 2013: The VME core has been tested in several
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configurations, including on several different boards
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([VFC](https://www.ohwr.org/project/fmc-vme-carrier/wiki) and
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[SVEC](https://www.ohwr.org/project/svec/wiki)) together in the same
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crate and with several other modules sending traffic at the same time.
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Basically to test this core we used our experience that we had built up
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when testing commercial VME boards. This also used DMA from the
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processor board used in the crate.
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The code has been developed by a company and then CERN had a student who
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worked for a year on it. We still would like to do a serious review of
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the code to make sure there are no hidden bugs and just to make it all a
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bit cleaner.
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It is a product that we will support as we will base all our SVEC
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designs on it. For example the [ADC100M
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mezzanine](https://www.ohwr.org/fmc-adc-100m14b4cha/wiki) that you sell
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will also be ported to the
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[SVEC](https://www.ohwr.org/project/svec/wiki) and will use the core.
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Recently we found some errors and corrected them in a few days as can be
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seen in the
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[Repository](https://www.ohwr.org/project/vme64x-core/tree/master). This
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was on Rev.194. From the commit comments in this same repository you can
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also quite well follow what is being changed.
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Resuming, yes it is a perfectly usable core:
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- The black box testing we've done is a proof that it is working
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pretty fine.
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- CERN's commitment to use it for all SVEC designs assures it will
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work and will be maintained in case we find any further bugs.
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We will also be happy to receive feedback from you when you'll dig into
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the code.
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-----
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## Technical
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### Q: Does the core support RORA mode (Release on Register Access)?
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The core does *not* support the RORA mode.
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Furthermore note that the Interrupter implemented has not a queue.
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You can implement a queue in your WB application and output a new
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interrupt request only after a read operation.
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This will be the equivalent of a RORA Interrupter.
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Q:In which FPGA is it possible to fit the vme64x core?
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### Q:In which FPGA is it possible to fit the vme64x core?
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We are testing the core in the following FPGA:
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\- Spartan 6
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Device: XC6SLX150T
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Package: FGG676
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Speed -3
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- Spartan 6
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- Device: XC6SLX150T
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- Package: FGG676
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- Speed -3
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<!-- end list -->
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\- Spartan 6
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Device: XC6SLX150T
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Package: FGG900
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Speed -3
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- Spartan 6
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- Device: XC6SLX150T
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- Package: FGG900
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- Speed -3
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You can also fit the vme64x core in a smaller FPGA like the Spartan 6
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XC6SLX9, package: FTG 256.
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