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# Frequently Asked Questions
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-----
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## General
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### Q: what is really the state of the design?
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During October to December 2017, the core (version 2) was tested on a
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SVEC card with the MEN A20 and MEN A25 masters.
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During October to December 2017, the core (version 2) was tested on a SVEC card with the MEN A20 and MEN A25 masters.
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This very core is used in the accelerators of CERN, is used in various configurations and is proven to be stable in many complex environments.
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## Technical
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### Q:How to port a design from v1.0 to v2.0?
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### Q: How to port a design from v1.0 to v2.0?
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The official top level entity for the vme64x core is xvme64x\_core,
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which has the vme, wb and configuration grouped in
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| ... | ... | @@ -31,7 +30,7 @@ the xvme64x\_core is instantiated. |
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For software compatibility, AM matching should be disabled by setting
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generic g\_DECODE\_AM to false.
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### Q:In which FPGA is it possible to fit the vme64x core?
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### Q: In which FPGA is it possible to fit the vme64x core?
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On the SVEC card (Spartan 6), the core needs less than 750 registers.
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| ... | ... | @@ -68,3 +67,6 @@ driver](https://www.ohwr.org/project/svec-sw/tree/master/) can also be |
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very helpful in understanding how you can do the configuration by
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writing to the Address Relocation Registers.
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---
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19 November 2019 |
