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### Q: what is really the state of the design?
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State in March 2013: The VME core has been tested in several
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configurations, including on several different boards
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([VFC](https://www.ohwr.org/project/fmc-vme-carrier/wiki) and
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[SVEC](https://www.ohwr.org/project/svec/wiki)) together in the same
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crate and with several other modules sending traffic at the same time.
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Basically to test this core we used our experience that we had built up
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when testing commercial VME boards. This also used DMA from the
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processor board used in the crate.
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The code has been developed by a company and then CERN had a student who
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worked for a year on it. We still would like to do a serious review of
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the code to make sure there are no hidden bugs and just to make it all a
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bit cleaner.
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It is a product that we will support as we will base all our SVEC
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designs on it. For example the [ADC100M
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mezzanine](https://www.ohwr.org/fmc-adc-100m14b4cha/wiki) that you sell
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will also be ported to the
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[SVEC](https://www.ohwr.org/project/svec/wiki) and will use the core.
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Recently we found some errors and corrected them in a few days as can be
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seen in the
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[Repository](https://www.ohwr.org/project/vme64x-core/tree/master). This
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was on Rev.194. From the commit comments in this same repository you can
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also quite well follow what is being changed.
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Resuming, yes it is a perfectly usable core:
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- The black box testing we've done is a proof that it is working
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pretty fine.
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- CERN's commitment to use it for all SVEC designs assures it will
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work and will be maintained in case we find any further bugs.
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We will also be happy to receive feedback from you when you'll dig into
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the code.
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May 2017: the core is still used for any design using the SVEC. You may
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follow any [outstanding
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issues](https://www.ohwr.org/project/vme64x-core/issues) (that don't
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stop us from using this core).
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During October to December 2017, the core (version 2) was tested on a
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SVEC card with the MEN A20 and MEN A25 masters.
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-----
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## Technical
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### Q: Does the core support RORA mode (Release on Register Access)?
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### Q:How to port a design from v1.0 to v2.0?
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The core does *not* support the RORA mode.
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Furthermore note that the Interrupter implemented has not a queue.
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You can implement a queue in your WB application and output a new
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interrupt request only after a read operation.
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This will be the equivalent of a RORA Interrupter.
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The official top level entity for the vme64x core is xvme64x\_core,
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which has the vme, wb and configuration grouped in
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records.
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The VME signals berr\_n and irq\_n are now active when set to '0' (like
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on a VME bus), while in version 1.0 they followed the polarity of the
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SVEC card.
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The generic g\_WB\_GRANULARITY was added in v2.0. For compatibility, it
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should be set to BYTE if the vme64x\_core is instantiated and to WORD if
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the xvme64x\_core is instantiated.
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For software compatibility, AM matching should be disabled by setting
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generic g\_DECODE\_AM to false.
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### Q:In which FPGA is it possible to fit the vme64x core?
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On the SVEC card (Spartan 6), the core needs less than 750 registers.
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We are testing the core in the following FPGA:
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- Spartan 6
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### Q: What are the VME address modifiers supported by the core?
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Officially we support only:
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- A24 and A32 with 32-bit data width, supervisor mode (0x09 and 0x39).
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- Single, MBLT, BLT transfers.
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- The A32 window has size of 0x1000000 and is fixed to Function 0.
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- The A24 window's size is 0x80000 and it's attached to Function 1.
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This is the default setup in `VME_CR_pack.vhd`.
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Certain other modes (A16, unaligned/byte/halfword accesses) are
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implemented in the VHDL but have not been fully
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tested.
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- A24: AM 0x38 to 0x3f
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- A32: AM 0x08 to 0x0f
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- CS/CSR: AM
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0x2f
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### Q: I use the SVEC. How can I change the base address by writing appropriate values in some registers (ADER, ADEM, and possibly others)?
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Probably the example in the documentation of the
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[VME64xCore](https://www.ohwr.org/project/vme64x-core/commits/master/documentation/user_guides/vme64x_user_manual.pdf)
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of the SVEC is the most helpful in this, as it contains worked
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examples.
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Write the ADER registers with the address base and the AM.
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In addition, the code of [svec\_setup\_csr() in the svec device
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driver](https://www.ohwr.org/project/svec-sw/tree/master/) can also be
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very helpful in understanding how you can do the configuration by
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