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- [guidelines to use the vme64x
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core](https://www.ohwr.org/project/vme64x-core/blob/master/trunk/documentation/user_guides/python_test.pdf)
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## Contacts
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### General question about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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-----
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## Project Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>01-04-2010</td>
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<td>Start working on project.</td>
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</tr>
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<tr class="odd">
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<td>25-05-2010</td>
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<td>First HDL release.</td>
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</tr>
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<tr class="even">
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<td>10-02-2011</td>
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<td>First register read/write made with the core on the VFC.</td>
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</tr>
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<tr class="odd">
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<td>01-02-2012</td>
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<td>New student will work full time on project.</td>
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</tr>
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<tr class="even">
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<td>03-05-2012</td>
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<td>Core has been modified to implement CSR space. CSR and single R/W working on [VFC V2](https://www.ohwr.org/project/fmc-vme-carrier/wiki).</td>
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</tr>
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<tr class="odd">
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<td>10-05-2012</td>
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<td>Working on BLT, MBLT and 2eSST implementation.</td>
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</tr>
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<tr class="even">
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<td>06-06-2012</td>
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<td>Added data swap modes. A64, 2eVME and 2eSST not yet implemented. Independent tester added to team.</td>
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</tr>
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<tr class="odd">
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<td>30-07-2012</td>
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<td>SINGLE, BLT (D32), MBLT (D64) transfers in A16, A24, A32 and A64 address modes working on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided.</td>
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</tr>
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</tbody>
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</table>
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-----
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Davide Pedretti 30 July 2012
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