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@@ -6,10 +6,10 @@ The VME64x core implements a VME64 slave on one side and a WishBone
 master on the other without FIFOs in-between.
 
 The core supports SINGLE, BLT (D32), MBLT (D64) transfers in A24 and A32
-address modes and D08 (OE), D16, D32, D64 data transfers. The core can
-be configured via implemented CR/CSR configuration space. A ROACK type
-IRQ controller with one interrupt input and a programmable interrupt
-level and Status/ID register is provided.
+address modes and D08 (OE), D16, D32 data transfers. The core can be
+configured via implemented CR/CSR configuration space. A ROACK type IRQ
+controller with one interrupt input and a programmable interrupt level
+and Status/ID register is provided.
 
 A WishBone side features a pipelined WB
 master.
@@ -26,10 +26,10 @@ master.
         programmable interrupt level and Status/ID register
       - Supported VME access modes
           - SINGLE, BLT (D32), MBLT (D64)
-          - A24 and A32 address modes and D08 (OE), D16, D32, D64 data
+          - A24 and A32 address modes and D08 (OE), D16, D32 data
             transfers
   - WishBone master (user side)
-      - Pipelined WB master.
+      - Pipelined/Non-pipelined WB master.
 
 -----
 
@@ -153,6 +153,10 @@ on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided.</td>
 <td>02-10-2017</td>
 <td>Work completed.</td>
 </tr>
+<tr class="odd">
+<td>14-12-2017</td>
+<td>Release 2.0</td>
+</tr>
 </tbody>
 </table>