... | ... | @@ -6,10 +6,10 @@ The VME64x core implements a VME64 slave on one side and a WishBone |
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master on the other without FIFOs in-between.
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The core supports SINGLE, BLT (D32), MBLT (D64) transfers in A24 and A32
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address modes and D08 (OE), D16, D32, D64 data transfers. The core can
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be configured via implemented CR/CSR configuration space. A ROACK type
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IRQ controller with one interrupt input and a programmable interrupt
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level and Status/ID register is provided.
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address modes and D08 (OE), D16, D32 data transfers. The core can be
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configured via implemented CR/CSR configuration space. A ROACK type IRQ
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controller with one interrupt input and a programmable interrupt level
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and Status/ID register is provided.
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A WishBone side features a pipelined WB
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master.
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... | ... | @@ -26,10 +26,10 @@ master. |
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programmable interrupt level and Status/ID register
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- Supported VME access modes
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- SINGLE, BLT (D32), MBLT (D64)
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- A24 and A32 address modes and D08 (OE), D16, D32, D64 data
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- A24 and A32 address modes and D08 (OE), D16, D32 data
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transfers
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- WishBone master (user side)
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- Pipelined WB master.
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- Pipelined/Non-pipelined WB master.
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-----
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... | ... | @@ -153,6 +153,10 @@ on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided.</td> |
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<td>02-10-2017</td>
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<td>Work completed.</td>
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</tr>
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<tr class="odd">
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<td>14-12-2017</td>
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<td>Release 2.0</td>
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</tr>
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</tbody>
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</table>
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