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tom-bridge-nov27
9d52c5c1
·
adding missing files
·
Dec 11, 2019
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tom-cvora-feb10
ffa531dc
·
vme_bus: don't go to CHECK_TRANSFER_TYPE if DS inactive, causes an infinite loop
·
Feb 11, 2020
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tg-prefetch
48a4a5db
·
vme_funct_match: fix the function priority encoder.
·
Apr 15, 2020
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cvora-jul15
6d2b770e
·
hdl: improved static generation of ADER regsisters (non-64x mode with base address switch)
·
Jul 15, 2020
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tom-svec7
833193f0
·
rtl: some renaming in bridged mode: master -> SYS(FPGA), slave->APP(FPGA)
·
Sep 06, 2021
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tom-rf
42f6c768
·
HDL: fixes in the verilog wrapper of the core
·
Sep 13, 2022
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sowarzan-rf
02a397d1
·
hdl/rtl/xvme64x_core.vhd | hdl/rtl/vme64x_core_verilog.vhd add default return for functions
·
Dec 20, 2022
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tg-vme-master
54f127fe
·
tb_master: test burst reads
·
Jul 03, 2024
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