Use Verible for Verilog formatting

Much of the Verilog formatting seems to be broken. It could just be the difference between using tabs/spaces but some of it is hard to read.

I'd suggest using a tool such as the Verible Verilog formatter, verible-verilog-format. I use this along with some other whitespace fixers inside of pre-commit which might make it easy to integrate.

Just thought I'd start a conversation to discuss before starting any work.

If you haven't come across these tools before: https://pre-commit.com/ https://github.com/chipsalliance/verible/blob/master/verilog/tools/formatter/README.md