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Commit b0272366 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : added 5 kHzclock to padding function 

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/src_clkpadding/clkpadding_config.txt
	new file:   fpga/sources/src_clkpadding/clkpadding_padding.vhdl
	modified:   fpga/sources/src_clkpadding/clkpadding_top.vhdl
	modified:   fpga/sources/top.vhdl
	modified:   pcb/gerber/Transcode Report.txt
parent 30ac37b7
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fpga/TimEX3/TimEX3_eeprom.mcs
View file @ b0272366
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fpga/sources/src_clkpadding/clkpadding_config.txt
View file @ b0272366
......@@ -7,14 +7,14 @@
-- File : clkpadding_config.txt
-- Revision : x.x.x
-- Created : September 19, 2014
-- Updated : November 28, 2014
-- Updated : October 02, 2018
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
-- Copyright (C) 2012 - 2018 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -41,11 +41,11 @@ Configuration : clock padding
SW : 5-4-3-2-1-0
0-0-0-1-1-0
IO0 : input - monitored clock signal
IO1 : input - storage ring clock signal
IO2 : output - padded clock signal
IO3 : output - padded clock signal
IO4 : output - monitored clock signal
IO0 : input - monitored 1kHz clock signal
IO1 : input - monitored 5kHz clock signal
IO2 : output - padded 1kHz clock signal
IO3 : output - padded 5kHz clock signal
IO4 : output - not used ; to zero
Green LED on = OK
Red LED on = padding going on
......
fpga/sources/src_clkpadding/clkpadding_padding.vhdl 0 → 100755
View file @ b0272366
--------------------------------------------------------------------------------
-- Title : clock padding
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : clock padding
--------------------------------------------------------------------------------
-- File : clkpadding_top.vhdl
-- Revision : x.x.x
-- Created : July 19, 2014
-- Updated : October 02, 2018
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2018 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity clkpadding_padding is
generic (
g_gap_detect : unsigned (15 downto 0);
g_padding_period : unsigned (15 downto 0);
g_pulse_high : unsigned (15 downto 0)
);
port (
p_clkPADDING_clk500mHz : in std_logic;
p_clkPADDING_clk60MHz : in std_logic;
p_clkPADDING_clk_mon : in std_logic; -- monitored clock
p_clkPADDING_reset : in std_logic; -- global reset
p_clkPADDING_outTTL : out std_logic; -- TTL output ; output clock
p_clkPADDING_LED : out std_logic
);
end entity clkpadding_padding;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_clkpadding_padding of clkpadding_padding is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt1 : unsigned (15 downto 0); -- counter
signal s_cnt2 : unsigned (15 downto 0); -- counter
signal s_start : std_logic;
signal s_underProgress : std_logic;
signal s_clkPadding : std_logic;
signal s_clk_OUT : std_logic;
signal s_reset : std_logic;
signal s_extCLKup : std_logic;
signal s_led : std_logic;
signal s_ledHold : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- Detection of a gap in the input clock
process (p_clkPADDING_reset, s_reset, p_clkPADDING_clk60MHz)
begin
if ((p_clkPADDING_reset = '1') or (s_reset = '1')) then
s_cnt1 <= (OTHERS => '0');
s_start <= '0';
elsif (rising_edge(p_clkPADDING_clk60MHz)) then
if (s_cnt1 = g_gap_detect) then
s_start <= '1';
s_cnt1 <= s_cnt1;
else
s_cnt1 <= s_cnt1 + 1;
end if;
end if;
end process;
-- Generation of a padding clock if a gap is detected
-- in the input clock
process (p_clkPADDING_reset, p_clkPADDING_clk60MHz, p_clkPADDING_clk_mon)
begin
if (p_clkPADDING_reset = '1') then
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= '0';
elsif (rising_edge(p_clkPADDING_clk60MHz)) then
if (s_start = '1') then
s_cnt2 <= s_cnt2 + 1;
if (s_cnt2 < g_pulse_high) then
s_clkPadding <= '1';
elsif (s_cnt2 < g_padding_period) then
s_clkPadding <= '0';
else
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= '0';
end if;
else
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= '0';
end if;
end if;
end process;
-- Reset the padding if the external clock is on
process (p_clkPADDING_reset, s_reset, p_clkPADDING_clk_mon)
begin
if ((p_clkPADDING_reset = '1') or (s_reset = '1')) then
s_extCLKup <= '0';
elsif (rising_edge(p_clkPADDING_clk_mon)) then
s_extCLKup <= '1';
end if;
end process;
process (p_clkPADDING_reset, p_clkPADDING_clk60MHz)
begin
if (p_clkPADDING_reset = '1') then
s_reset <= '0';
elsif (rising_edge(p_clkPADDING_clk60MHz)) then
if (s_extCLKup = '1') then
s_reset <= '1';
else
s_reset <= '0';
end if;
end if;
end process;
-- Multiplex the output according to the input state
with s_start select
s_clk_OUT <=
s_clkPadding when '1',
p_clkPADDING_clk_mon when OTHERS;
-- Trigger red LED
process (p_clkPADDING_reset, s_start, p_clkPADDING_clk500mHz)
begin
if ((p_clkPADDING_reset = '1') or (s_start = '1')) then
s_led <= '1';
s_ledHold <= '1';
elsif (rising_edge(p_clkPADDING_clk500mHz)) then
s_led <= s_ledHold;
s_ledHold <= '0';
end if;
end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_clkPADDING_outTTL <= s_clk_OUT;
p_clkPADDING_LED <= s_led; -- red LED
end architecture rtl_clkpadding_padding;
fpga/sources/src_clkpadding/clkpadding_top.vhdl
View file @ b0272366
......@@ -2,24 +2,33 @@
-- Title : Top - clock padding function
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : generate a 1 kHz clock on the output whenever the input 1 kHz
-- clock is missing on the input.
-- Description : generate a 1 kHz clock on the output whenever 1 kHz input
-- clock is missing.
-- It is used by Cristal laser synchro system to avoid gaps in the
-- 1 kHz clock when changing delays
-- The laser frequency is :
-- Fl = Frf / 2 / 0x2AF60 = 1000.7397555 Hz (999.261 s)
-- The input is on pin_inTTL(0) ; the output is on pin_outTTL(2)
--
-- generate a 5 kHz clock on the output whenever 5 kHz input
-- clock is missing.
-- It is used by Cristal laser synchro system to avoid gaps in the
-- 5 kHz clock when changing delays
-- The laser frequency is :
-- Fl = Frf / 2 / 0x8950 = 5009.701 Hz (199.613 s)
-- The input is on pin_inTTL(1) ; the output is on pin_outTTL(3)
--------------------------------------------------------------------------------
-- File : clkpadding_top.vhdl
-- Revision : x.x.x
-- Created : July 19, 2014
-- Updated : November 27, 2015
-- Updated : October 02, 2018
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
-- Copyright (C) 2012 - 2018 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -51,8 +60,8 @@ entity clkPADDING_top is
port (
p_clkPADDING_clk500mHz : in std_logic;
p_clkPADDING_clk60MHz : in std_logic;
p_clkPADDING_clk_mon : in std_logic; -- monitored clock
p_clkPADDING_aux_IN : in std_logic; -- auxilairy input (not used)
p_clkPADDING_1kHz_mon : in std_logic; -- 1 kHz monitored clock
p_clkPADDING_5kHz_mon : in std_logic; -- 5 kHz monitored clock
p_clkPADDING_reset : in std_logic; -- global reset
p_clkPADDING_outTTL : out std_logic_vector (4 downto 0); -- TTL outputs -- output clock
p_clkPADDING_outPECL : out std_logic_vector (4 downto 0); -- LVPECL outputs
......@@ -68,124 +77,60 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant c_gapDetect : unsigned (15 downto 0) := X"EA36"; -- 59958
constant c_paddingPeriod : unsigned (15 downto 0) := X"EA34"; -- 59956
constant c_pulseHigh : unsigned (15 downto 0) := X"2EE0"; -- 12000 => 200 s
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt1 : unsigned (15 downto 0); -- counter
signal s_cnt2 : unsigned (15 downto 0); -- counter
signal s_start : std_logic;
signal s_underProgress : std_logic;
signal s_clkPadding : std_logic;
signal s_clk_OUT : std_logic;
signal s_reset : std_logic;
signal s_extCLKup : std_logic;
signal s_led : std_logic;
signal s_ledHold : std_logic;
signal s_clkPADDING_LED_1khHz : std_logic;
signal s_clkPADDING_LED_5khHz : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- Detection of a gap in the input clock
process (p_clkPADDING_reset, s_reset, p_clkPADDING_clk60MHz)
begin
if ((p_clkPADDING_reset = '1') or (s_reset = '1')) then
s_cnt1 <= (OTHERS => '0');
s_start <= '0';
elsif (rising_edge(p_clkPADDING_clk60MHz)) then
if (s_cnt1 = c_gapDetect) then
s_start <= '1';
s_cnt1 <= s_cnt1;
else
s_cnt1 <= s_cnt1 + 1;
end if;
end if;
end process;
-- Generation of a padding clock if a gap is detected
-- in the input clock
process (p_clkPADDING_reset, p_clkPADDING_clk60MHz, p_clkPADDING_clk_mon)
begin
if (p_clkPADDING_reset = '1') then
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= '0';
elsif (rising_edge(p_clkPADDING_clk60MHz)) then
if (s_start = '1') then
s_cnt2 <= s_cnt2 + 1;
if (s_cnt2 < c_pulseHigh) then
s_clkPadding <= '1';
elsif (s_cnt2 < c_paddingPeriod) then
s_clkPadding <= '0';
else
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= '0';
end if;
else
s_cnt2 <= (OTHERS => '0');
s_clkPadding <= '0';
end if;
end if;
end process;
-- Reset the padding if the external clock is on
process (p_clkPADDING_reset, s_reset, p_clkPADDING_clk_mon)
begin
if ((p_clkPADDING_reset = '1') or (s_reset = '1')) then
s_extCLKup <= '0';
elsif (rising_edge(p_clkPADDING_clk_mon)) then
s_extCLKup <= '1';
end if;
end process;
process (p_clkPADDING_reset, p_clkPADDING_clk60MHz)
begin
if (p_clkPADDING_reset = '1') then
s_reset <= '0';
elsif (rising_edge(p_clkPADDING_clk60MHz)) then
if (s_extCLKup = '1') then
s_reset <= '1';
else
s_reset <= '0';
end if;
end if;
end process;
-- Multiplex the output according to the input state
with s_start select
s_clk_OUT <=
s_clkPadding when '1',
p_clkPADDING_clk_mon when OTHERS;
-- 1kHz clock padding
padding_1kHz : entity work.clkpadding_padding (rtl_clkpadding_padding)
generic map (
g_gap_detect => X"EA36", -- 59958 ; (59958 + 1) / 60e6 = 999.317 s
-- 1 kHz period = 999.261 s
g_padding_period => X"EA34", -- 59956 ; 59956 / 60e6 = 999.267 s
g_pulse_high => X"2EE0") -- 12000 => 200 s
port map (
p_clkPADDING_clk500mHz => p_clkPADDING_clk500mHz,
p_clkPADDING_clk60MHz => p_clkPADDING_clk60MHz,
p_clkPADDING_clk_mon => p_clkPADDING_1kHz_mon, -- monitored clock
p_clkPADDING_reset => p_clkPADDING_reset, -- global reset
p_clkPADDING_outTTL => p_clkPADDING_outTTL(2), -- TTL outputs ; output clock
p_clkPADDING_LED => s_clkPADDING_LED_1khHz
);
-- Trigger red LED
process (p_clkPADDING_reset, s_start, p_clkPADDING_clk500mHz)
begin
if ((p_clkPADDING_reset = '1') or (s_start = '1')) then
s_led <= '1';
s_ledHold <= '1';
elsif (rising_edge(p_clkPADDING_clk500mHz)) then
s_led <= s_ledHold;
s_ledHold <= '0';
end if;
end process;
-- 5kHz clock padding
padding_5kHz : entity work.clkpadding_padding (rtl_clkpadding_padding)
generic map (
g_gap_detect => X"2ED2", -- 11986 ; (11986 + 1) / 60e6 = 199.783 s
-- 5 kHz period = 199.613 s
g_padding_period => X"2EC9", -- 11977 ; 11977 / 60e6 = 199.617 s
g_pulse_high => X"2EE0" ) -- 12000 => 200 s
port map (
p_clkPADDING_clk500mHz => p_clkPADDING_clk500mHz,
p_clkPADDING_clk60MHz => p_clkPADDING_clk60MHz,
p_clkPADDING_clk_mon => p_clkPADDING_5kHz_mon, -- monitored clock
p_clkPADDING_reset => p_clkPADDING_reset, -- global reset
p_clkPADDING_outTTL => p_clkPADDING_outTTL(3), -- TTL outputs ; output clock
p_clkPADDING_LED => s_clkPADDING_LED_5khHz
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_clkPADDING_outTTL(0) <= '0'; -- not used ; is configured as input
p_clkPADDING_outTTL(1) <= '0'; -- not used ; is configured as input
p_clkPADDING_outTTL(2) <= s_clk_OUT;
p_clkPADDING_outTTL(3) <= s_clk_OUT;
p_clkPADDING_outTTL(4) <= s_clk_OUT;
p_clkPADDING_outTTL(4) <= '0'; -- not used
p_clkPADDING_outPECL(4 downto 0) <= "00000";
p_clkPADDING_led(0) <= s_led; -- red LED
p_clkPADDING_led(1) <= '1'; -- green LED ON
p_clkPADDING_led(0) <= s_clkPADDING_LED_1khHz or s_clkPADDING_LED_5khHz; -- red LED
p_clkPADDING_led(1) <= '1'; -- green LED ON
end architecture rtl_clkPADDING_top;
fpga/sources/top.vhdl
View file @ b0272366
......@@ -7,14 +7,14 @@
-- File : top.vhd
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : November 27, 2015
-- Updated : October 02, 2018
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
-- Copyright (C) 2012 - 2018 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -63,6 +63,8 @@
-- * Corrected a mistak in clock padding function
-- Version 1.9.5 ; November 27, 2015 ; Jean-Paul Ricaud
-- * Removed the usage of the CLK_SR in clock padding function
-- Version 1.9.6 ; October 02, 2018 ; Jean-Paul Ricaud
-- * Added a 5 kHz clock padding option
--
--------------------------------------------------------------------------------
......@@ -586,8 +588,8 @@ architecture rtl_top of top is
port map (
p_clkPADDING_clk500mHz => s_clk500mhz,
p_clkPADDING_clk60MHz => s_clk60MHz,
p_clkPADDING_clk_mon => pin_inTTL(0),
p_clkPADDING_aux_IN => pin_inTTL(1),
p_clkPADDING_1kHz_mon => pin_inTTL(0),
p_clkPADDING_5kHz_mon => pin_inTTL(1),
p_clkPADDING_reset => s_reset,
p_clkPADDING_outTTL => s_clkPaddingOutTTL,
p_clkPADDING_outPECL => s_clkPaddingOutPECL,
......
pcb/gerber/Transcode Report.txt
View file @ b0272366
......@@ -721,4 +721,226 @@ D53 --> D364
D54 --> D365
D55 --> D366
D56 --> D367
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123f1.274x' ---- Tue Apr 19 14:38:26 2016
D10 --> D100
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123pa1.274x' ---- Fri Apr 29 13:33:22 2016
D10 --> D100
D11 --> D101
D12 --> D102
D13 --> D103
D14 --> D104
D15 --> D105
D16 --> D106
D17 --> D107
D18 --> D108
D19 --> D109
D20 --> D110
D21 --> D111
D22 --> D112
D23 --> D113
D24 --> D114
D25 --> D115
D26 --> D116
D27 --> D117
D28 --> D118
D29 --> D119
D30 --> D120
D31 --> D121
D32 --> D122
D33 --> D123
D34 --> D124
D35 --> D125
D36 --> D126
D37 --> D127
D38 --> D128
D39 --> D129
D40 --> D130
D41 --> D131
D42 --> D132
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123s1.274x' ---- Fri Apr 29 13:34:45 2016
D10 --> D133
D11 --> D134
D12 --> D135
D13 --> D60
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123v1.274x' ---- Fri Apr 29 13:35:13 2016
D10 --> D136
D11 --> D137
D12 --> D138
D13 --> D139
D14 --> D140
D15 --> D141
D16 --> D142
D17 --> D143
D18 --> D144
D19 --> D145
D20 --> D146
D21 --> D147
D22 --> D148
D23 --> D149
D24 --> D150
D25 --> D151
D26 --> D152
D27 --> D153
D28 --> D154
D29 --> D155
D30 --> D156
D31 --> D157
D32 --> D158
D33 --> D159
D34 --> D160
D35 --> D161
D36 --> D162
D37 --> D163
D38 --> D164
D39 --> D165
D40 --> D166
D41 --> D167
D42 --> D168
D43 --> D169
D44 --> D170
D45 --> D171
D46 --> D172
D47 --> D173
D48 --> D174
D49 --> D175
D50 --> D176
D51 --> D177
D52 --> D178
D53 --> D179
D54 --> D180
D55 --> D181
D56 --> D182
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123f1.274x' ---- Fri Apr 29 15:54:06 2016
D10 --> D100
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123met.274x' ---- Fri Apr 29 16:29:32 2016
D10 --> D66
D11 --> D100
D12 --> D101
D14 --> D102
D15 --> D103
D16 --> D104
D17 --> D65
D18 --> D105
D19 --> D106
D20 --> D107
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\plan.274x' ---- Fri Apr 29 16:29:54 2016
D10 --> D108
D11 --> D109
D12 --> D110
D13 --> D111
D14 --> D112
D15 --> D113
D16 --> D114
D17 --> D115
D18 --> D116
D19 --> D117
D20 --> D118
D21 --> D119
D22 --> D120
D23 --> D121
D24 --> D122
D25 --> D123
D26 --> D124
D27 --> D125
D28 --> D126
D29 --> D127
D30 --> D128
D32 --> D129
D33 --> D130
D34 --> D131
D35 --> D132
D37 --> D133
D38 --> D134
D39 --> D135
D40 --> D136
D42 --> D137
D43 --> D138
D44 --> D139
D45 --> D140
D47 --> D141
D48 --> D142
D49 --> D143
D50 --> D144
D52 --> D145
D53 --> D146
-----------------------------------------------------------------
---- Transcoding 'D:\jpr\projets\TimEX3\pcb\gerber\45123v1.274x' ---- Fri Apr 29 16:30:24 2016
D10 --> D147
D11 --> D148
D12 --> D149
D13 --> D150
D14 --> D151
D15 --> D152
D16 --> D153
D17 --> D154
D18 --> D155
D19 --> D156
D20 --> D157
D21 --> D158
D22 --> D159
D23 --> D160
D24 --> D161
D25 --> D162
D26 --> D163
D27 --> D164
D28 --> D165
D29 --> D166
D30 --> D167
D31 --> D168
D32 --> D169
D33 --> D170
D34 --> D171
D35 --> D172
D36 --> D173
D37 --> D174
D38 --> D175
D39 --> D176
D40 --> D177
D41 --> D178
D42 --> D64
D43 --> D179
D44 --> D180
D45 --> D181
D46 --> D182
D47 --> D183
D48 --> D184
D49 --> D185
D50 --> D186
D51 --> D187
D52 --> D188
D53 --> D189
D54 --> D190
D55 --> D191
D56 --> D192
-----------------------------------------------------------------
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