external interlock signal was added to the top level of the TimEX3 FPGA
code

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
	modified:   fpga/sources/top.vhdl