• Jean-Paul Ricaud's avatar
    VHDL : added frequency divider block for slicing synchro DG · 4563b9be
    Jean-Paul Ricaud authored
     On branch development
    
    	modified:   fpga/sources/outputmux.vhdl
    	modified:   fpga/sources/registers_init.vhdl
    	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
    	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
    	modified:   fpga/sources/src_duplication/dup_leds.vhdl
    	new file:   fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl
    	new file:   fpga/sources/src_freqDIV/freqDIV_config.txt
    	new file:   fpga/sources/src_freqDIV/freqDIV_leds.vhdl
    	new file:   fpga/sources/src_freqDIV/freqDIV_monitoring.vhdl
    	new file:   fpga/sources/src_freqDIV/freqDIV_top.vhdl
    	modified:   fpga/sources/src_linacMON/linacMON_leds.vhdl
    	modified:   fpga/sources/src_linacMP/linacMP_leds.vhdl
    	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
    	modified:   fpga/sources/src_topup/topup_gating.vhdl
    	modified:   fpga/sources/top.vhdl
    	modified:   fpga/sources/type_lib.vhdl
    4563b9be
cPCI_registerMux.vhdl 12.5 KB