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Commit 2c5f641b authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : removed DCM block from the frequency divider function as it is no 

more used and it is needed elsewhere

 On branch development

	modified:   fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl
parent b75b921d
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fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl
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......@@ -9,7 +9,7 @@
-- File : freqDIV_clkdiv.vhd
-- Revision : x.x.x
-- Created : February 03, 2014
-- Updated : February 25, 2015
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -74,11 +74,10 @@ architecture rtl_freqDIV_clkdiv of freqDIV_clkdiv is
signal s_lfsr_lsb : std_logic;
signal s_div_423 : std_logic;
signal s_1k_SR : std_logic;
signal s_1k_8bunch : std_logic;
signal s_clk8bunch : std_logic;
signal s_cnt : unsigned (15 downto 0); -- counter
signal GND_BIT : std_logic;
-- signal s_1k_8bunch : std_logic;
-- signal s_clk8bunch : std_logic;
-- signal s_cnt : unsigned (15 downto 0); -- counter
-- signal GND_BIT : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
......@@ -114,79 +113,79 @@ architecture rtl_freqDIV_clkdiv of freqDIV_clkdiv is
end process;
------------------------------------------------------------------------------
-------------------------- 8 bunch laser clock -------------------------------
-- DCM_SP: Digital Clock Manager
-- Spartan-6
-- Xilinx HDL Language Template, version 14.4
GND_BIT <= '0';
DCM_SP_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- CLKDV divide value
-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => 8, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 999.9, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "NONE", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DSS_MODE => "NONE", -- Unsupported - Do not change value
DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
FACTORY_JF => X"c080", -- Unsupported - Do not change value
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
CLK0 => open, -- 1-bit output: 0 degree clock output
CLK180 => open, -- 1-bit output: 180 degree clock output
CLK270 => open, -- 1-bit output: 270 degree clock output
CLK2X => open, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => open, -- 1-bit output: 90 degree clock output
CLKDV => open, -- 1-bit output: Divided clock output
CLKFX => s_clk8bunch, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
LOCKED => open, -- 1-bit output: DCM_SP Lock Output
PSDONE => open, -- 1-bit output: Phase shift done output
STATUS => open, -- 8-bit output: DCM_SP status output
CLKFB => GND_BIT, -- 1-bit input: Clock feedback input
CLKIN => p_clkSR, -- 1-bit input: Clock input
DSSEN => GND_BIT, -- 1-bit input: Unsupported, specify to GND.
PSCLK => GND_BIT, -- 1-bit input: Phase shift clock input
PSEN => GND_BIT, -- 1-bit input: Phase shift enable
PSINCDEC => GND_BIT, -- 1-bit input: Phase shift increment/decrement input
RST => p_reset -- 1-bit input: Active high reset input
);
process (p_reset, s_clk8bunch)
begin
if (p_reset = '1') then
s_cnt <= (OTHERS => '0');
elsif (rising_edge(s_clk8bunch)) then
if (s_cnt = c_8bunch_period) then
s_cnt <= (OTHERS => '0');
else
s_cnt <= s_cnt + 1;
end if;
end if;
end process;
process (p_reset, s_clk8bunch)
begin
if (p_reset = '1') then
s_1k_8bunch <= '1';
elsif (rising_edge(s_clk8bunch)) then
if (s_cnt < c_8bunch_period_high) then
s_1k_8bunch <= '1';
else
s_1k_8bunch <= '0';
end if;
end if;
end process;
-- -------------------------- 8 bunch laser clock -------------------------------
-- -- DCM_SP: Digital Clock Manager
-- -- Spartan-6
-- -- Xilinx HDL Language Template, version 14.4
--
-- GND_BIT <= '0';
--
-- DCM_SP_inst : DCM_SP
-- generic map (
-- CLKDV_DIVIDE => 2.0, -- CLKDV divide value
-- -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
-- CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
-- CLKFX_MULTIPLY => 8, -- Multiply value on CLKFX outputs - M - (2-32)
-- CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
-- CLKIN_PERIOD => 999.9, -- Input clock period specified in nS
-- CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
-- CLK_FEEDBACK => "NONE", -- Feedback source (NONE, 1X, 2X)
-- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
-- DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
-- DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
-- DSS_MODE => "NONE", -- Unsupported - Do not change value
-- DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
-- FACTORY_JF => X"c080", -- Unsupported - Do not change value
-- PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
-- STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
-- )
-- port map (
-- CLK0 => open, -- 1-bit output: 0 degree clock output
-- CLK180 => open, -- 1-bit output: 180 degree clock output
-- CLK270 => open, -- 1-bit output: 270 degree clock output
-- CLK2X => open, -- 1-bit output: 2X clock frequency clock output
-- CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
-- CLK90 => open, -- 1-bit output: 90 degree clock output
-- CLKDV => open, -- 1-bit output: Divided clock output
-- CLKFX => s_clk8bunch, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
-- CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
-- LOCKED => open, -- 1-bit output: DCM_SP Lock Output
-- PSDONE => open, -- 1-bit output: Phase shift done output
-- STATUS => open, -- 8-bit output: DCM_SP status output
-- CLKFB => GND_BIT, -- 1-bit input: Clock feedback input
-- CLKIN => p_clkSR, -- 1-bit input: Clock input
-- DSSEN => GND_BIT, -- 1-bit input: Unsupported, specify to GND.
-- PSCLK => GND_BIT, -- 1-bit input: Phase shift clock input
-- PSEN => GND_BIT, -- 1-bit input: Phase shift enable
-- PSINCDEC => GND_BIT, -- 1-bit input: Phase shift increment/decrement input
-- RST => p_reset -- 1-bit input: Active high reset input
-- );
--
-- process (p_reset, s_clk8bunch)
-- begin
-- if (p_reset = '1') then
-- s_cnt <= (OTHERS => '0');
-- elsif (rising_edge(s_clk8bunch)) then
-- if (s_cnt = c_8bunch_period) then
-- s_cnt <= (OTHERS => '0');
-- else
-- s_cnt <= s_cnt + 1;
-- end if;
-- end if;
-- end process;
--
-- process (p_reset, s_clk8bunch)
-- begin
-- if (p_reset = '1') then
-- s_1k_8bunch <= '1';
-- elsif (rising_edge(s_clk8bunch)) then
-- if (s_cnt < c_8bunch_period_high) then
-- s_1k_8bunch <= '1';
-- else
-- s_1k_8bunch <= '0';
-- end if;
-- end if;
-- end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......@@ -195,8 +194,10 @@ architecture rtl_freqDIV_clkdiv of freqDIV_clkdiv is
p_clkOUT(1) <= s_1k_SR;
p_clkOUT(2) <= s_1k_SR;
p_clkOUT(3) <= s_1k_8bunch;
p_clkOUT(4) <= s_1k_8bunch;
p_clkOUT(3) <= s_1k_SR;
p_clkOUT(4) <= s_1k_SR;
-- p_clkOUT(3) <= s_1k_8bunch;
-- p_clkOUT(4) <= s_1k_8bunch;
-- Unused signals
p_clkOUT(0) <= '0'; -- the IO is used as input
......
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