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TimEX3
Commit b75b921d authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : improved top-up gating and beam lost detection 

 On branch development

	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/src_MIK/MIK_detection.vhdl
	modified:   fpga/sources/src_MIK/MIK_duplication.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
parent 09d84b4d
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Showing with 62 additions and 58 deletions
fpga/TimEX3/top.ucf
View file @ b75b921d
......@@ -7,14 +7,14 @@
# File : top.ucf
# Revision : x.x.x
# Created : October 29, 2012
# Updated : October 29, 2013
# Updated : April 29, 2015
################################################################################
# Author : Jean-Paul Ricaud
# Organization : Synchrotron Soleil
# Web : http://www.synchrotron-soleil.fr
# Email : jean-paul.ricaud@synchrotron-soleil.fr
################################################################################
# Copyright (C) 2012 - 2013 Synchrotron Soleil
# Copyright (C) 2012 - 2015 Synchrotron Soleil
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
......@@ -311,8 +311,13 @@ NET "pin_LWRn" SLEW = FAST;
NET "pin_WRn" SLEW = FAST;
NET "pin_CLK60MHz" CLOCK_DEDICATED_ROUTE = TRUE;
NET "s_CLK60MHz" CLOCK_DEDICATED_ROUTE = TRUE;
NET "s_clk60MHz" CLOCK_DEDICATED_ROUTE = TRUE;
NET "pin_inTTL[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "pin_CLK60MHz" TNM_NET = "pin_CLK60MHz";
TIMESPEC TS_pin_CLK60MHz = PERIOD "pin_CLK60MHz" 60 MHz HIGH 50 % INPUT_JITTER 50 ps;
NET "pin_outTTL[1]" OFFSET = OUT 14 ns AFTER "pin_CLK60MHz" RISING;
NET "pin_outTTL[2]" OFFSET = OUT 14 ns AFTER "pin_CLK60MHz" RISING;
NET "pin_outTTL[3]" OFFSET = OUT 14 ns AFTER "pin_CLK60MHz" RISING;
NET "pin_outTTL[4]" OFFSET = OUT 14 ns AFTER "pin_CLK60MHz" RISING;
fpga/sources/src_MIK/MIK_detection.vhdl
View file @ b75b921d
......@@ -62,9 +62,13 @@ end MIK_detection;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture rtl_MIK_detection of MIK_detection is
-----------------------------------------------------------------------------
-- constant
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- signal
-----------------------------------------------------------------------------
signal s_resync : std_logic_vector (2 downto 0);
-- s_risingEdge : std_logic;
-- s_fallingEdge : std_logic;
......@@ -73,10 +77,6 @@ architecture rtl_MIK_detection of MIK_detection is
signal s_start : std_logic;
signal s_end : std_logic;
signal s_rstCNT : std_logic;
signal s_delayed : std_logic_vector (4 downto 1);
attribute keep : string;
attribute keep of s_delayed : signal is "True";
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
......@@ -96,11 +96,11 @@ architecture rtl_MIK_detection of MIK_detection is
end process;
-- Start
process (p_reset, s_end, s_resync(0))
process (p_reset, s_end, s_resync(2))
begin
if ((p_reset = '1') or (s_end ='1')) then
s_start <= '0';
elsif (rising_edge(s_resync(0))) then
elsif (rising_edge(s_resync(2))) then
s_start <= '1';
else
s_start <= s_start;
......
fpga/sources/src_MIK/MIK_duplication.vhdl
View file @ b75b921d
......@@ -7,7 +7,7 @@
-- File : MIK_duplication.vhd
-- Revision : x.x.x
-- Created : April 28, 2015
-- Updated : April 28, 2015
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -56,56 +56,24 @@ end MIK_duplication;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture rtl_MIK_duplication of MIK_duplication is
-----------------------------------------------------------------------------
-- constant
constant c_lenght_delayedOut4 : integer := 8;
constant c_lenght_delayedOut3 : integer := 6;
constant c_lenght_delayedOut2 : integer := 4;
constant c_lenght_delayedOut1 : integer := 2;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- signal
signal s_delayedOut4 : std_logic_vector (c_lenght_delayedOut4 downto 0);
signal s_delayedOut3 : std_logic_vector (c_lenght_delayedOut3 downto 0);
signal s_delayedOut2 : std_logic_vector (c_lenght_delayedOut2 downto 0);
signal s_delayedOut1 : std_logic_vector (c_lenght_delayedOut1 downto 0);
attribute keep : string;
attribute keep of s_delayedOUT1 : signal is "True";
attribute keep of s_delayedOUT2 : signal is "True";
attribute keep of s_delayedOUT3 : signal is "True";
attribute keep of s_delayedOUT4 : signal is "True";
-----------------------------------------------------------------------------
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
s_delayedOut4(0) <= not p_in;
genDelay4 : for i in 1 to (c_lenght_delayedOut4) generate
begin
s_delayedOut4(i) <= not s_delayedOut4(i - 1);
end generate genDelay4;
p_outTTL(4) <= not s_delayedOut4(c_lenght_delayedOut4);
s_delayedOut3(0) <= not p_in;
genDelay3 : for i in 1 to (c_lenght_delayedOut3) generate
begin
s_delayedOut3(i) <= not s_delayedOut3(i - 1);
end generate genDelay3;
p_outTTL(3) <= not s_delayedOut3(c_lenght_delayedOut3);
p_outTTL(4) <= not p_in;
p_outTTL(3) <= not p_in;
p_outTTL(2) <= not p_in;
p_outTTL(1) <= not p_in;
s_delayedOut2(0) <= not p_in;
genDelay2 : for i in 1 to (c_lenght_delayedOut2) generate
begin
s_delayedOut2(i) <= not s_delayedOut2(i - 1);
end generate genDelay2;
p_outTTL(2) <= not s_delayedOut2(c_lenght_delayedOut2);
s_delayedOut1(0) <= not p_in;
genDelay1 : for i in 1 to (c_lenght_delayedOut1) generate
begin
s_delayedOut1(i) <= not s_delayedOut1(i - 1);
end generate genDelay1;
p_outTTL(1) <= not s_delayedOut1(c_lenght_delayedOut1);
-- Unused signals
p_outTTL(0) <= '0'; -- the IO is used as input
......
fpga/sources/src_duplication/dup_top.vhdl
View file @ b75b921d
......@@ -36,7 +36,7 @@
--------------------------------------------------------------------------------
-- Modifications :
-- Version 1.2.1 ; June 14 2013 ; Jean-Paul Ricaud
-- * Added deay on duplicated outputs to compensate the outputs offsets
-- * Added delay on duplicated outputs to compensate the outputs offsets
--
--------------------------------------------------------------------------------
......@@ -162,6 +162,7 @@ architecture rtl_dup_top of dup_top is
s_delayedOut1(i) <= not s_delayedOut1(i - 1);
end generate genDelay1;
p_dup_outTTL(1) <= not s_delayedOut1(c_lenght_delayedOut1);
-- p_dup_outTTL(1) <= s_dup_outTTL(1);
end architecture rtl_dup_top;
fpga/sources/src_topup/topup_beamlost.vhdl
View file @ b75b921d
......@@ -18,7 +18,7 @@
-- File : topup_beamlost.vhdl
-- Revision : x.x.x
-- Created : April 12, 2013
-- Updated : October 29, 2013
-- Updated : April 29, 2015
-------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -83,6 +83,9 @@ architecture rtl_topup_beamlost of topup_beamlost is
-----------------------------------------------------------------------------
-- signal
-----------------------------------------------------------------------------
signal s_resync : std_logic_vector (2 downto 0);
-- s_risingEdge : std_logic;
-- s_fallingEdge : std_logic;
signal s_beamLost : std_logic;
signal s_cntHoldOff : unsigned (31 downto 0);
signal s_holdOffMax : unsigned (31 downto 0);
......@@ -105,13 +108,25 @@ architecture rtl_topup_beamlost of topup_beamlost is
-----------------------------------------------------------------------------
begin
-- Resync input
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_resync <= "000";
elsif (rising_edge(p_clk60MHz)) then
s_resync <= s_resync (1 downto 0) & p_inTTL(0);
-- s_risingEdge <= s_resync(1) and not s_resync(2);
-- s_fallingEdge <= s_resync(2) and not s_resync(1);
end if;
end process;
-- Create a reset pulse at each pre top-up signal received
-- p_inTTL(0) = pre top-up
process (p_reset, s_rst, p_inTTL(0))
process (p_reset, s_rst, s_resync(2))
begin
if ((p_reset = '1') or (s_rst = '1')) then
s_rstCycle <= '0';
elsif (rising_edge(p_inTTL(0))) then
elsif (rising_edge(s_resync(2))) then
s_rstCycle <= '1'; -- injection occurred, reset cycle
else
s_rstCycle <= s_rstCycle;
......
fpga/sources/src_topup/topup_gating.vhdl
View file @ b75b921d
......@@ -14,14 +14,14 @@
-- File : topup_gating.vhdl
-- Revision : x.x.x
-- Created : December 05, 2012
-- Updated : February 03, 2014
-- Updated : April 29, 2015
-------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
-------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -76,6 +76,9 @@ architecture rtl_topup_gating of topup_gating is
-----------------------------------------------------------------------------
-- signal
-----------------------------------------------------------------------------
signal s_resync : std_logic_vector (2 downto 0);
-- s_risingEdge : std_logic;
-- s_fallingEdge : std_logic;
signal s_holdOffStart : std_logic;
signal s_cntHoldOff : unsigned (31 downto 0);
signal s_cntHoldOffMax : unsigned (31 downto 0);
......@@ -96,12 +99,24 @@ architecture rtl_topup_gating of topup_gating is
-----------------------------------------------------------------------------
begin
-- Resync input
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_resync <= "000";
elsif (rising_edge(p_clk60MHz)) then
s_resync <= s_resync (1 downto 0) & p_inTTL(0);
-- s_risingEdge <= s_resync(1) and not s_resync(2);
-- s_fallingEdge <= s_resync(2) and not s_resync(1);
end if;
end process;
-- Start a gating cycle on a pre top-up trigger on p_inTTL(0)
process (p_reset, s_gateEnd, p_inTTL(0))
process (p_reset, s_gateEnd, s_resync(2))
begin
if ((p_reset = '1') or (s_gateEnd ='1')) then
s_holdOffStart <= '0';
elsif (rising_edge(p_inTTL(0))) then
elsif (rising_edge(s_resync(2))) then
s_holdOffStart <= '1'; -- pre top-up
else
s_holdOffStart <= s_holdOffStart;
......
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