Tags · Projects / TimEX3 · GitLab

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1.9.5

30ac37b7 · Added the FPGA binary · Jan 08, 2016
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version 1.9.5
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1.9.1

73240c33 · PCB : added modified gerber files (better mask screens) ; old gerber · Feb 24, 2015
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version 1.9.1
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1.9.0

79badd9e · BOM : added manufacturer classified BOM · Jan 16, 2015
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version 1.9.0
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1.6.1

618e1548 · Added CAD drawing for frequency divider option and binaries files. · Mar 07, 2014
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version 1.6.1
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1.6.0

28062311 · VHDL : code cleanup · Dec 09, 2013
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version 1.6.0
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1.4.0

8e21f2e8 · FPGA : updated the EEPROM binairies with LINAC functions · Aug 09, 2013
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version 1.4.0
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1.2.1

5182c64f · VHDL : Compensated output offsets in duplication mode · Jun 17, 2013
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version 1.2.1
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1.2.0

00d1ee91 · VHDL : updated the topup_config.txt file to reflect the new outputs · Apr 26, 2013
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version 1.2.0
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1.0.0

c012f785 · typo correction · Apr 09, 2013
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version 1.0.0
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