--------------------------------------------------------------------------------
-- Title   : Output Mutiplexer
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : Output multiplexer
--  SW 5-4-3-2-1-0
--     1-1-1-1-1-1 : board test
--     0-0-0-1-1-0 : clock padding
--     0-0-0-1-0-1 : LINAC synchonized interlock
--     0-0-0-1-0-0 : frequency divider
--     0-0-0-0-1-1 : LINAC monitoring
--     0-0-0-0-1-0 : LINAC multipulse
--     0-0-0-0-0-1 : top-up trigger
--     0-0-0-0-0-0 : duplication
--------------------------------------------------------------------------------
-- File     : outputmux.vhdl
-- Revision : x.x.x
-- Created  : October 26, 2012
-- Updated  : December 01, 2014
--------------------------------------------------------------------------------
-- Author       : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web          : http://www.synchrotron-soleil.fr
-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--   Version 1.4.0 ; July 09 2013 ; Jean-Paul Ricaud
--     * Added LINAC monitoring function
--   Version 1.6.1 ; February 03 2014 ; Jean-Paul Ricaud
--     * Added frequency divider block for slicing DG
--   Version 1.8.0 ; September 19 2014 ; Jean-Paul Ricaud
--     * Added clock padding for CRISTAL beamline laser syncgrinization
--   Version 1.9.0 ; November 28 2014 ; Jean-Paul Ricaud
--     * Changed the configuration switch of the clock padding from
--         0-0-0-1-0-1 to 0-0-0-1-1-0
--     * Added synchronized interlock of the LINAC's synchronization signals
--
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity outputMux is
  port (
    -- Duplication block
    p_dup_outTTL       : in std_logic_vector (4 downto 0);
    p_dup_outPECL      : in std_logic_vector (4 downto 0);
    p_dup_LED          : in std_logic_vector (1 downto 0);
    -- Top-up block
    p_topup_outTTL     : in std_logic_vector (4 downto 0);
    p_topUp_outPECL    : in std_logic_vector (4 downto 0);
    p_topUp_LED        : in std_logic_vector (1 downto 0);
    -- LINAC multipulse block
    p_linacMP_outTTL   : in std_logic_vector (4 downto 0);
    p_linacMP_outPECL  : in std_logic_vector (4 downto 0);
    p_linacMP_LED      : in std_logic_vector (1 downto 0);
    -- LINAC monitoring block
    p_linacMON_outTTL  : in std_logic_vector (4 downto 0);
    p_linacMON_outPECL : in std_logic_vector (4 downto 0);
    p_linacMON_LED     : in std_logic_vector (1 downto 0);
    -- Freaquency divider block
    p_freqDIV_outTTL   : in std_logic_vector (4 downto 0);
    p_freqDIV_outPECL  : in std_logic_vector (4 downto 0);
    p_freqDIV_LED      : in std_logic_vector (1 downto 0);
    -- LINAC synchronized interlock block
    p_linacSYNCLOCK_outTTL  : in std_logic_vector (4 downto 0);
    p_linacSYNCLOCK_outPECL : in std_logic_vector (4 downto 0);
    p_linacSYNCLOCK_LED     : in std_logic_vector (1 downto 0);
    -- clock padding block
    p_clkPADDING_outTTL  : in std_logic_vector (4 downto 0);
    p_clkPADDING_outPECL : in std_logic_vector (4 downto 0);
    p_clkPADDING_LED     : in std_logic_vector (1 downto 0);
    -- Test block
    p_test_outTTL      : in std_logic_vector (4 downto 0);
    p_test_outPECL     : in std_logic_vector (4 downto 0);
    p_test_LED         : in std_logic_vector (1 downto 0);
    -- Mux block
    p_mux_SWsel        : in  std_logic_vector (5 downto 0);
    p_mux_outTTL       : out std_logic_vector (4 downto 0);
    p_mux_outPECL      : out std_logic_vector (4 downto 0);
    p_mux_outLED       : out std_logic_vector (1 downto 0)
  );
end entity outputMux;

--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_outputMux of outputMux is
  ------------------------------------------------------------------------------
  -- constant
  ------------------------------------------------------------------------------

  ------------------------------------------------------------------------------
  -- signal
  ------------------------------------------------------------------------------

  ------------------------------------------------------------------------------
  -- Components
  ------------------------------------------------------------------------------

  ------------------------------------------------------------------------------
  --------------------------------- Main ---------------------------------------
  ------------------------------------------------------------------------------
  begin

  -- TTL ouuputs selection
  with p_mux_SWsel select
    p_mux_outTTL <=
      p_dup_outTTL           when "000000",
      p_topUp_outTTL         when "000001",
      p_linacMP_outTTL       when "000010",
      p_linacMON_outTTL      when "000011",
      p_freqDIV_outTTL       when "000100",
      p_linacSYNCLOCK_outTTL when "000101",
      p_clkPADDING_outTTL    when "000110",
      p_test_outTTL          when OTHERS;

  -- LVPECL ouuputs selection
  with p_mux_SWsel select
    p_mux_outPECL <=
      p_dup_outPECL           when "000000",
      p_topUp_outPECL         when "000001",
      p_linacMP_outPECL       when "000010",
      p_linacMON_outPECL      when "000011",
      p_freqDIV_outPECL       when "000100",
      p_linacSYNCLOCK_outPECL when "000101",
      p_clkPADDING_outPECL    when "000110",
      p_test_outPECL          when OTHERS;

  -- LEDs outputs selection
  with p_mux_SWsel select
    p_mux_outLED <=
      p_dup_LED           when "000000",
      p_topUp_LED         when "000001",
      p_linacMP_LED       when "000010",
      p_linacMON_LED      when "000011",
      p_freqDIV_LED       when "000100",
      p_linacSYNCLOCK_LED when "000101",
      p_clkPADDING_LED    when "000110",
      p_test_LED          when OTHERS;

  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
end architecture rtl_outputMux;

