--------------------------------------------------------------------------------
-- Title   : clock padding test bench
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : CRISTAL clock padding test bench
--------------------------------------------------------------------------------
-- File     : clkPADDING_td.vhdl
-- Revision : x.x.x
-- Created  : July 19, 2014
-- Updated  : Septembre 19, 2014
--------------------------------------------------------------------------------
-- Author       : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web          : http://www.synchrotron-soleil.fr
-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity clkPADDING_tb is
end entity clkPADDING_tb;

--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture simu_clkPADDING_tb of clkPADDING_tb is
  ------------------------------------------------------------------------------
  -- constant
  ------------------------------------------------------------------------------
  constant period_846kHz : TIME := 1181.16 ns;
  constant period_1kHz   : TIME := 999260.79 ns;
  constant delta         : TIME := 171736 ns;
  constant shortDelta    : TIME := 4600 ns;
  constant delta50u      : TIME := 50000 ns;

  ------------------------------------------------------------------------------
  -- signal
  ------------------------------------------------------------------------------
  signal s_reset      : std_logic;
  signal s_clk500mHz  : std_logic;
  signal s_clkSR      : std_logic;
  signal s_clkTimBeL  : std_logic;
  signal s_clkoutTTL  : std_logic_vector (4 downto 0);
  signal s_clkoutPECL : std_logic_vector (4 downto 0);
  signal s_outLED     : std_logic_vector (1 downto 0);

  signal s_chgMark    : std_logic;

  ------------------------------------------------------------------------------
  --------------------------------- Main ---------------------------------------
  ------------------------------------------------------------------------------
  begin

  DUT : entity work.clkPADDING_top (rtl_clkPADDING_top)
    port map (
      p_clkPADDING_clk500mHz => s_clk500mHz,
      p_clkPADDING_clk_mon   => s_clkTimBeL,
      p_clkPADDING_clk_sr    => s_clkSR,
      p_clkPADDING_reset     => s_reset,
      p_clkPADDING_outTTL    => s_clkoutTTL,
      p_clkPADDING_outPECL   => s_clkoutPECL,
      p_clkPADDING_LED       => s_outLED
    );

  -- Clock generator
  process
  begin
    s_clkSR <= '0';
    wait for (period_846kHz / 2);
    s_clkSR <= '1';
    wait for (period_846kHz / 2);
  end process;

  process
  begin
    s_clk500mHz <= '0';
    wait for (period_1kHz);
    s_clk500mHz <= '1';
    wait for (period_1kHz);
  end process;
  

  process
  begin
    -- Reset
    s_clkTimBeL <= '0';
    s_reset     <= '0';
    s_chgMark   <= '0';
    wait for 5 ns;
    s_reset <= '1';
    wait for 5 ns;
    s_reset <= '0';
    wait for 5 ns;

    ---------------------------
    ---------------------------
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';

    ---------------------------
    ---------------------------
    s_chgMark   <= '1';
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for (period_1kHz);
    wait for delta;
    s_chgMark   <= '0';

    ---------------------------
    ---------------------------
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for delta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';

    ---------------------------
    ---------------------------
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for shortDelta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for shortDelta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for shortDelta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for shortDelta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for shortDelta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for shortDelta;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';

    ---------------------------
    ---------------------------
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for (period_1kHz * 2);
    wait for delta50u;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';

    ---------------------------
    ---------------------------
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 4);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    ---------------------------
    s_chgMark   <= '1';
    wait for (period_1kHz * 2);
    wait for delta50u;
    s_clkTimBeL <= '1';
    s_chgMark   <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '1';
    wait for (period_1kHz / 2);
    s_clkTimBeL <= '0';

    -- *** END ***
    wait;
  end process;

  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------

end architecture simu_clkPADDING_tb;
