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-- Title   : Top - frequency division function
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : Top sheet of the frequency division block
--    inTTL(0) is the CLK_SR provided by a LOCAL borad. This clk is dided by 846
--    outTTL are CLK_SR / 846
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-- File     : freqDIV_top.vhdl
-- Revision : x.x.x
-- Created  : February 03, 2014
-- Updated  : February 03, 2014
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-- Author       : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web          : http://www.synchrotron-soleil.fr
-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
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-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity freqDiv_top is
  port (
    p_freqDIV_inTTL             : in  std_logic;                     -- input TTL
    p_freqDIV_outTTL            : out std_logic_vector (4 downto 0); -- TTL outputs
    p_freqDIV_outPECL           : out std_logic_vector (4 downto 0); -- LVPECL outputs
    p_freqDIV_clk1kHz           : in  std_logic;
    p_freqDIV_clk500mHz         : in  std_logic;
    p_freqDIV_clk60MHz          : in  std_logic;
    p_freqDIV_missingPulseDelay : in  std_logic_vector (31 downto 0);
    p_freqDIV_csw               : in  std_logic;
    p_freqDIV_reset             : in  std_logic;
    p_freqDIV_pulseMon          : out std_logic_vector (31 downto 0); -- pulses monitor
    p_freqDIV_led               : out std_logic_vector (1 downto 0)
  );
end entity freqDiv_top;

--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_freqDiv_top of freqDiv_top is

  ------------------------------------------------------------------------------
  -- constant
  ------------------------------------------------------------------------------

  ------------------------------------------------------------------------------
  -- signal
  ------------------------------------------------------------------------------

  ------------------------------------------------------------------------------
  --------------------------------- Main ---------------------------------------
  ------------------------------------------------------------------------------
  begin

    -- Frequency divider : Fout = 1000.7558192399 Hz = CLK_SR / 846 = slicing laser freq
    slicingFreq : entity work.freqDIV_clkdiv (rtl_freqDIV_clkdiv)
      port map (
        p_clkSR   => p_freqDIV_inTTL,  -- TTL in
        p_reset   => p_freqDIV_reset,  -- reset
        p_clkOUT  => p_freqDIV_outTTL, -- TTL out
        p_outPECL => p_freqDIV_outPECL -- LVPECL out
      );

    -- Signal monitoring block
    -- The time betwwen 2 input pulses in stored in MONITOR register (in ms)
    pulseMonitor : entity work.freqDIV_monitoring (rtl_freqDIV_monitoring)
      port map (
        p_inTTL   => p_freqDIV_inTTL,    -- TTL input
        p_clk1kHz => p_freqDIV_clk1kHz,
        p_reset   => p_freqDIV_reset,
        p_monitor => p_freqDIV_pulseMon  -- register with the time value between two pulses
      );

    -- LEDs management for the duplication block
    -- The green LED is blinked for 5s after a reset or after a input pulse is
    -- détected. It remains ON in other cases.
    -- The red LED is off after a reset. It gos ON if no input signal is detected
    -- after delay defined in the missingPulseDelay register.
    leds : entity work.freqDIV_leds (rtl_freqDIV_leds)
      port map (
        p_inTTL             => p_freqDIV_inTTL,  -- TTL input
        p_clk1kHz           => p_freqDIV_clk1kHz,
        p_clk500mHz         => p_freqDIV_clk500mHz,
        p_clk60MHz          => p_freqDIV_clk60MHz,
        p_missingPulseDelay => p_freqDIV_missingPulseDelay,
        p_csw               => p_freqDIV_csw,
        p_reset             => p_freqDIV_reset,
        p_led               => p_freqDIV_led
      );

  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------

end architecture rtl_freqDiv_top;
