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TDC core
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TDC core
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8b4fd4d7
Commit
8b4fd4d7
authored
Aug 20, 2011
by
Sebastien Bourdeauducq
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doc: TIG constraint
parent
25797851
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doc/tdc.tex
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8b4fd4d7
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@@ -62,6 +62,11 @@ R(n) = \frac{f_{0}}{f} \cdot R_{0}(n)
\subsection
{
Deskew stage
}
\section
{
Implementing the core
}
\begin{verbatim}
NET "cmp
_
channelbank/g
_
channels[0].cmp
_
channel/muxed
_
signal" TIG;
\end{verbatim}
\begin{thebibliography}
{
99
}
\bibitem
{
s6hdl
}
Xilinx,
\textsl
{
Spartan-6 Libraries Guide for HDL Designs
}
,
\url
{
http://www.xilinx.com/support/documentation/sw
_
manuals/xilinx12
_
3/spartan6
_
hdl.pdf
}
\bibitem
{
epfl
}
Claudio Favi and Edoardo Charbon,
\textsl
{
A 17ps Time-to-Digital Converter Implemented in 65nm FPGA Technology
}
, ACM 2009,
\url
{
http://infoscience.epfl.ch/record/139431
}
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