doc: TIG constraint

8b4fd4d7 · Sebastien Bourdeauducq · 25797851 · 8b4fd4d7
Commit 8b4fd4d7 authored Aug 20, 2011 by Sebastien Bourdeauducq
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tdc.tex doc/tdc.tex +5 -0

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--- a/doc/tdc.tex
+++ b/doc/tdc.tex
@@ -62,6 +62,11 @@ R(n) = \frac{f_{0}}{f} \cdot R_{0}(n)

 \subsection{Deskew stage}

+\section{Implementing the core}
+\begin{verbatim}
+NET "cmp_channelbank/g_channels[0].cmp_channel/muxed_signal" TIG;
+\end{verbatim}
+
 \begin{thebibliography}{99}
 \bibitem{s6hdl} Xilinx, \textsl{Spartan-6 Libraries Guide for HDL Designs}, \url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/spartan6_hdl.pdf}
 \bibitem{epfl} Claudio Favi and Edoardo Charbon, \textsl{A 17ps Time-to-Digital Converter Implemented in 65nm FPGA Technology}, ACM 2009, \url{http://infoscience.epfl.ch/record/139431}