doc: TIG constraint

parent 25797851
......@@ -62,6 +62,11 @@ R(n) = \frac{f_{0}}{f} \cdot R_{0}(n)
\subsection{Deskew stage}
\section{Implementing the core}
NET "cmp_channelbank/g_channels[0].cmp_channel/muxed_signal" TIG;
\bibitem{s6hdl} Xilinx, \textsl{Spartan-6 Libraries Guide for HDL Designs}, \url{}
\bibitem{epfl} Claudio Favi and Edoardo Charbon, \textsl{A 17ps Time-to-Digital Converter Implemented in 65nm FPGA Technology}, ACM 2009, \url{}
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