Skip to content

S
Simple VME FMC Carrier SVEC
Commit ed0566a9 authored by Matthieu Cattin's avatar Matthieu Cattin
Browse files
Options

Add afpga ucf for pcb v1.

parent 8e3c04b1
Hide whitespace changes
Inline Side-by-side
Showing with 1270 additions and 0 deletions
hdl/top/ddr_test/svec_v1_afpga.ucf 0 → 100644
View file @ ed0566a9
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_sysreset_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = V3;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_gap_n_i" LOC = M6;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_d_oe_n_o" LOC = P1;
NET "vme_d_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_a_oe_n_o" LOC = N4;
NET "vme_a_dir_o" LOC = N5;
NET "vme_irq_n_o[7]" LOC = R7;
NET "vme_irq_n_o[6]" LOC = AH2;
NET "vme_irq_n_o[5]" LOC = AF2;
NET "vme_irq_n_o[4]" LOC = N9;
NET "vme_irq_n_o[3]" LOC = N10;
NET "vme_irq_n_o[2]" LOC = AH4;
NET "vme_irq_n_o[1]" LOC = AG4;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_d_b[31]" LOC = AK3;
NET "vme_d_b[30]" LOC = AH3;
NET "vme_d_b[29]" LOC = T8;
NET "vme_d_b[28]" LOC = T9;
NET "vme_d_b[27]" LOC = AK4;
NET "vme_d_b[26]" LOC = AJ4;
NET "vme_d_b[25]" LOC = W6;
NET "vme_d_b[24]" LOC = W7;
NET "vme_d_b[23]" LOC = AB6;
NET "vme_d_b[22]" LOC = AB7;
NET "vme_d_b[21]" LOC = W9;
NET "vme_d_b[20]" LOC = W10;
NET "vme_d_b[19]" LOC = AK5;
NET "vme_d_b[18]" LOC = AH5;
NET "vme_d_b[17]" LOC = AD6;
NET "vme_d_b[16]" LOC = AC6;
NET "vme_d_b[15]" LOC = AA6;
NET "vme_d_b[14]" LOC = AA7;
NET "vme_d_b[13]" LOC = T6;
NET "vme_d_b[12]" LOC = T7;
NET "vme_d_b[11]" LOC = AG5;
NET "vme_d_b[10]" LOC = AE5;
NET "vme_d_b[9]" LOC = Y11;
NET "vme_d_b[8]" LOC = W11;
NET "vme_d_b[7]" LOC = AF6;
NET "vme_d_b[6]" LOC = AE6;
NET "vme_d_b[5]" LOC = Y8;
NET "vme_d_b[4]" LOC = Y9;
NET "vme_d_b[3]" LOC = AE7;
NET "vme_d_b[2]" LOC = AD7;
NET "vme_d_b[1]" LOC = AA9;
NET "vme_d_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_a_b[31]" LOC = T2;
NET "vme_a_b[30]" LOC = T3;
NET "vme_a_b[29]" LOC = T4;
NET "vme_a_b[28]" LOC = U1;
NET "vme_a_b[27]" LOC = U3;
NET "vme_a_b[26]" LOC = U4;
NET "vme_a_b[25]" LOC = U5;
NET "vme_a_b[24]" LOC = V1;
NET "vme_a_b[23]" LOC = V2;
NET "vme_a_b[22]" LOC = W1;
NET "vme_a_b[21]" LOC = W3;
NET "vme_a_b[20]" LOC = AA4;
NET "vme_a_b[19]" LOC = AA5;
NET "vme_a_b[18]" LOC = Y1;
NET "vme_a_b[17]" LOC = Y2;
NET "vme_a_b[16]" LOC = Y3;
NET "vme_a_b[15]" LOC = Y4;
NET "vme_a_b[14]" LOC = AC1;
NET "vme_a_b[13]" LOC = AC3;
NET "vme_a_b[12]" LOC = AD1;
NET "vme_a_b[11]" LOC = AD2;
NET "vme_a_b[10]" LOC = AB3;
NET "vme_a_b[9]" LOC = AB4;
NET "vme_a_b[8]" LOC = AD3;
NET "vme_a_b[7]" LOC = AD4;
NET "vme_a_b[6]" LOC = AC4;
NET "vme_a_b[5]" LOC = AC5;
NET "vme_a_b[4]" LOC = N7;
NET "vme_a_b[3]" LOC = N8;
NET "vme_a_b[2]" LOC = AE1;
NET "vme_a_b[1]" LOC = AE3;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "clk20_vcxo_i" LOC = V26;
#NET "fpga_clk_n_i" LOC = AB30;
#NET "fpga_clk_p_i" LOC = AB28;
#NET "si57x_clk_n_i" LOC = W28;
#NET "si57x_clk_p_i" LOC = W27;
#NET "pll_2afpga_n_i" LOC = AA1;
#NET "pll_2afpga_p_i" LOC = AA3;
#----------------------------------------
# Switches and button
#----------------------------------------
#NET "pushbutton_i" LOC = P24;
#NET "noga_i[0]" LOC = AE26;
#NET "noga_i[1]" LOC = P23;
#NET "noga_i[2]" LOC = Y24;
#NET "noga_i[3]" LOC = Y23;
#NET "noga_i[4]" LOC = V23;
#NET "switch_i[0]" LOC = W22;
#NET "switch_i[1]" LOC = W21;
#NET "usega_i" LOC = Y22;
#----------------------------------------
# Inter-FPGA lines
#----------------------------------------
#NET "rsvd_b[0]" LOC = AG26;
#NET "rsvd_b[1]" LOC = AH26;
#NET "rsvd_b[2]" LOC = AG27;
#NET "rsvd_b[3]" LOC = AH27;
#NET "rsvd_b[4]" LOC = AK27;
#NET "rsvd_b[5]" LOC = AG28;
#NET "rsvd_b[6]" LOC = AJ28;
#NET "rsvd_b[7]" LOC = AK28;
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[4]" LOC = AF17;
NET "pcbrev_i[3]" LOC = AE17;
NET "pcbrev_i[2]" LOC = AD18;
NET "pcbrev_i[1]" LOC = AE20;
NET "pcbrev_i[0]" LOC = AD20;
#----------------------------------------
# SFP slot
#----------------------------------------
#NET "sfprx_123_n_i" LOC = C22;
#NET "sfprx_123_p_i" LOC = D22;
#NET "sfptx_123_n_o" LOC = A23;
#NET "sfptx_123_p_o" LOC = B23;
#NET "gtp_ck1_p_i" LOC = B19;
#NET "gtp_ck1_n_i" LOC = A19;
#NET "wr_los_i" LOC = W25;
#NET "wr_moddef0_i" LOC = Y26;
#NET "wr_moddef1_o" LOC = Y27;
#NET "wr_moddef2_b" LOC = AA24;
#NET "wr_rateselect_o" LOC = W24;
#NET "wr_txdisable_o" LOC = AA25;
#NET "wr_txfault_i" LOC = AA27;
#----------------------------------------
# SATA connectors
#----------------------------------------
#NET "sata1_tx_p_o" LOC = AJ9;
#NET "sata1_tx_n_o" LOC = AK9;
#NET "sata1_rx_p_i" LOC = AG10;
#NET "sata1_rx_n_i" LOC = AH10;
#NET "sata0_tx_p_o" LOC = AJ11;
#NET "sata0_tx_n_o" LOC = AK11;
#NET "sata0_rx_p_i" LOC = AG12;
#NET "sata0_rx_n_i" LOC = AH12;
#NET "gtp_ck0_p_i" LOC = AJ13;
#NET "gtp_ck0_n_i" LOC = AK13;
#----------------------------------------
# PCIe interface (optional)
#----------------------------------------
#NET "pcie_tx1_p_o" LOC = B11;
#NET "pcie_tx1_n_o" LOC = A11;
#NET "pcie_rx1_p_i" LOC = D12;
#NET "pcie_rx1_n_i" LOC = C12;
#NET "pcie_master_clk_p_i" LOC = D14;
#NET "pcie_master_clk_n_i" LOC = C14;
#----------------------------------------
# Clock controls
#----------------------------------------
#NET "oe_si57x_o" LOC = Y28;
#NET "si57x_scl_o" LOC = Y30;
#NET "si57x_sda_b" LOC = AA29;
#NET "si57x_tune_o" LOC = W30; # (optional)
#NET "pll20dac_din_o" LOC = U28;
#NET "pll20dac_sclk_o" LOC = AA28;
#NET "pll20dac_sync_n_o" LOC = N28;
#NET "pll25dac_din_o" LOC = P25;
#NET "pll25dac_sclk_o" LOC = N27;
#NET "pll25dac_sync_n_o" LOC = P26;
#----------------------------------------
# UART
#----------------------------------------
#NET "uart_rxd_o" LOC = U27;
#NET "uart_txd_i" LOC = U25;
#----------------------------------------
# USB (optional)
#----------------------------------------
#NET "usb_clkout_i" LOC = V24;
#NET "usb_oe_n_o" LOC = Y25;
#NET "usb_rd_n_o" LOC = T26;
#NET "usb_rxf_n_i" LOC = T24;
#NET "usb_siwua_i" LOC = U24;
#NET "usb_txe_n_i" LOC = T25;
#NET "usb_wr_n_o" LOC = T27;
#NET "usb_d_b[0]" LOC = P27;
#NET "usb_d_b[1]" LOC = R24;
#NET "usb_d_b[2]" LOC = R25;
#NET "usb_d_b[3]" LOC = R27;
#NET "usb_d_b[4]" LOC = R28;
#NET "usb_d_b[5]" LOC = R22;
#NET "usb_d_b[6]" LOC = P22;
#NET "usb_d_b[7]" LOC = R21;
#NET "io7_i" LOC = U30;
#----------------------------------------
# VME P2
#----------------------------------------
#NET "p2_data_p_b[19]" LOC = B7;
#NET "p2_data_p_b[18]" LOC = K10;
#NET "p2_data_p_b[17]" LOC = H17;
#NET "p2_data_p_b[16]" LOC = F8;
#NET "p2_data_p_b[15]" LOC = E7;
#NET "p2_data_p_b[14]" LOC = D6;
#NET "p2_data_p_b[13]" LOC = AE9;
#NET "p2_data_p_b[12]" LOC = AD8;
#NET "p2_data_p_b[11]" LOC = AG6;
#NET "p2_data_p_b[10]" LOC = AF7;
#NET "p2_data_p_b[9]" LOC = M10;
#NET "p2_data_p_b[8]" LOC = L17;
#NET "p2_data_p_b[7]" LOC = J8;
#NET "p2_data_p_b[6]" LOC = D8;
#NET "p2_data_p_b[5]" LOC = H7;
#NET "p2_data_p_b[4]" LOC = F6;
#NET "p2_data_p_b[3]" LOC = AH7;
#NET "p2_data_p_b[2]" LOC = AB10;
#NET "p2_data_p_b[1]" LOC = W12;
#NET "p2_data_p_b[0]" LOC = AA11;
#NET "p2_data_n_b[19]" LOC = A7;
#NET "p2_data_n_b[18]" LOC = J10;
#NET "p2_data_n_b[17]" LOC = G17;
#NET "p2_data_n_b[16]" LOC = E8;
#NET "p2_data_n_b[15]" LOC = D7;
#NET "p2_data_n_b[14]" LOC = C6;
#NET "p2_data_n_b[13]" LOC = AF9;
#NET "p2_data_n_b[12]" LOC = AE8;
#NET "p2_data_n_b[11]" LOC = AH6;
#NET "p2_data_n_b[10]" LOC = AG7;
#NET "p2_data_n_b[9]" LOC = L10;
#NET "p2_data_n_b[8]" LOC = K17;
#NET "p2_data_n_b[7]" LOC = H8;
#NET "p2_data_n_b[6]" LOC = C8;
#NET "p2_data_n_b[5]" LOC = G7;
#NET "p2_data_n_b[4]" LOC = E6;
#NET "p2_data_n_b[3]" LOC = AK7;
#NET "p2_data_n_b[2]" LOC = AB9;
#NET "p2_data_n_b[1]" LOC = Y12;
#NET "p2_data_n_b[0]" LOC = AB11;
#----------------------------------------
# DDR3 (bank 4)
#----------------------------------------
NET "ddr_zio_b" LOC = J6;
NET "ddr_rzq_b" LOC = L7;
NET "ddr_we_n_o" LOC = F4;
NET "ddr_udqs_p_b" LOC = K2;
NET "ddr_udqs_n_b" LOC = K1;
NET "ddr_udm_o" LOC = K4;
NET "ddr_reset_n_o" LOC = G5;
NET "ddr_ras_n_o" LOC = C1;
NET "ddr_odt_o" LOC = E4;
NET "ddr_ldqs_p_b" LOC = J5;
NET "ddr_ldqs_n_b" LOC = J4;
NET "ddr_ldm_o" LOC = K3;
NET "ddr_cke_o" LOC = C4;
NET "ddr_ck_p_o" LOC = E3;
NET "ddr_ck_n_o" LOC = E1;
NET "ddr_cas_n_o" LOC = B1;
NET "ddr_dq_b[15]" LOC = M1;
NET "ddr_dq_b[14]" LOC = M2;
NET "ddr_dq_b[13]" LOC = L1;
NET "ddr_dq_b[12]" LOC = L3;
NET "ddr_dq_b[11]" LOC = L4;
NET "ddr_dq_b[10]" LOC = L5;
NET "ddr_dq_b[9]" LOC = M3;
NET "ddr_dq_b[8]" LOC = M4;
NET "ddr_dq_b[7]" LOC = H1;
NET "ddr_dq_b[6]" LOC = H2;
NET "ddr_dq_b[5]" LOC = G1;
NET "ddr_dq_b[4]" LOC = G3;
NET "ddr_dq_b[3]" LOC = J1;
NET "ddr_dq_b[2]" LOC = J3;
NET "ddr_dq_b[1]" LOC = H3;
NET "ddr_dq_b[0]" LOC = H4;
NET "ddr_ba_o[2]" LOC = F3;
NET "ddr_ba_o[1]" LOC = D1;
NET "ddr_ba_o[0]" LOC = D2;
#NET "ddr_a_o[14]" LOC = A5;
NET "ddr_a_o[13]" LOC = B5;
NET "ddr_a_o[12]" LOC = A4;
NET "ddr_a_o[11]" LOC = G4;
NET "ddr_a_o[10]" LOC = D5;
NET "ddr_a_o[9]" LOC = A2;
NET "ddr_a_o[8]" LOC = B2;
NET "ddr_a_o[7]" LOC = B3;
NET "ddr_a_o[6]" LOC = F1;
NET "ddr_a_o[5]" LOC = F2;
NET "ddr_a_o[4]" LOC = C5;
NET "ddr_a_o[3]" LOC = E5;
NET "ddr_a_o[2]" LOC = A3;
NET "ddr_a_o[1]" LOC = D3;
NET "ddr_a_o[0]" LOC = D4;
#----------------------------------------
# DDR3 (bank 5)
#----------------------------------------
NET "ddr_2_zio_b" LOC = L24;
NET "ddr_2_rzq_b" LOC = G25;
NET "ddr_2_we_n_o" LOC = E26;
NET "ddr_2_udqs_p_b" LOC = K28;
NET "ddr_2_udqs_n_b" LOC = K30;
NET "ddr_2_udm_o" LOC = J27;
NET "ddr_2_reset_n_o" LOC = C26;
NET "ddr_2_ras_n_o" LOC = K26;
NET "ddr_2_odt_o" LOC = E30;
NET "ddr_2_ldqs_p_b" LOC = J29;
NET "ddr_2_ldqs_n_b" LOC = J30;
NET "ddr_2_ldm_o" LOC = J28;
NET "ddr_2_cke_o" LOC = B29;
NET "ddr_2_ck_p_o" LOC = E27;
NET "ddr_2_ck_n_o" LOC = E28;
NET "ddr_2_cas_n_o" LOC = K27;
NET "ddr_2_dq_b[15]" LOC = M30;
NET "ddr_2_dq_b[14]" LOC = M28;
NET "ddr_2_dq_b[13]" LOC = M27;
NET "ddr_2_dq_b[12]" LOC = M26;
NET "ddr_2_dq_b[11]" LOC = L30;
NET "ddr_2_dq_b[10]" LOC = L29;
NET "ddr_2_dq_b[9]" LOC = L28;
NET "ddr_2_dq_b[8]" LOC = L27;
NET "ddr_2_dq_b[7]" LOC = F30;
NET "ddr_2_dq_b[6]" LOC = F28;
NET "ddr_2_dq_b[5]" LOC = G28;
NET "ddr_2_dq_b[4]" LOC = G27;
NET "ddr_2_dq_b[3]" LOC = G30;
NET "ddr_2_dq_b[2]" LOC = G29;
NET "ddr_2_dq_b[1]" LOC = H30;
NET "ddr_2_dq_b[0]" LOC = H28;
NET "ddr_2_ba_o[2]" LOC = D26;
NET "ddr_2_ba_o[1]" LOC = C27;
NET "ddr_2_ba_o[0]" LOC = D27;
#NET "ddr_2_a_o[14]" LOC = A29;
NET "ddr_2_a_o[13]" LOC = A28;
NET "ddr_2_a_o[12]" LOC = B30;
NET "ddr_2_a_o[11]" LOC = A26;
NET "ddr_2_a_o[10]" LOC = F26;
NET "ddr_2_a_o[9]" LOC = A27;
NET "ddr_2_a_o[8]" LOC = B27;
NET "ddr_2_a_o[7]" LOC = C29;
NET "ddr_2_a_o[6]" LOC = H27;
NET "ddr_2_a_o[5]" LOC = H26;
NET "ddr_2_a_o[4]" LOC = F27;
NET "ddr_2_a_o[3]" LOC = E29;
NET "ddr_2_a_o[2]" LOC = C30;
NET "ddr_2_a_o[1]" LOC = D30;
NET "ddr_2_a_o[0]" LOC = D28;
#----------------------------------------
# FMC slot 1
#----------------------------------------
#NET "fmc1_gbtclk0m2c_p_i" LOC = B13;
#NET "fmc1_gbtclk0m2c_n_i" LOC = A13;
#NET "fmc1_dp0m2c_p_i" LOC = D10;
#NET "fmc1_dp0m2c_n_i" LOC = C10;
#NET "fmc1_dp0c2m_p_o" LOC = B9;
#NET "fmc1_dp0c2m_n_o" LOC = A9;
#NET "fmc1_pg_c2m_o" LOC = N29;
NET "fmc1_prsntm2c_n_i" LOC = N30;
#NET "fmc1_scl_o" LOC = P28;
#NET "fmc1_sda_b" LOC = P30;
#NET "fmc1_tck_o" LOC = AJ30;
#NET "fmc1_tdi_i" LOC = AG30;
#NET "fmc1_tdo_o" LOC = AF30;
#NET "fmc1_tms_o" LOC = AE25;
#########################################
# clk0m2c, clk1m2c and la0-la33 can be assigned automatically with ucfgen
#NET "fmc1_clk1m2c_p_i" LOC = E16;
#NET "fmc1_clk1m2c_n_i" LOC = D16;
#NET "fmc1_clk0m2c_p_i" LOC = H15;
#NET "fmc1_clk0m2c_n_I" LOC = G15;
#NET "fmc1_la_p_b[33]" LOC = J12;
#NET "fmc1_la_p_b[32]" LOC = H11;
#NET "fmc1_la_p_b[31]" LOC = L11;
#NET "fmc1_la_p_b[30]" LOC = J13;
#NET "fmc1_la_p_b[29]" LOC = F9;
#NET "fmc1_la_p_b[28]" LOC = L12;
#NET "fmc1_la_p_b[27]" LOC = M13;
#NET "fmc1_la_p_b[26]" LOC = L14;
#NET "fmc1_la_p_b[25]" LOC = F11;
#NET "fmc1_la_p_b[24]" LOC = G10;
#NET "fmc1_la_p_b[23]" LOC = M15;
#NET "fmc1_la_p_b[22]" LOC = F13;
#NET "fmc1_la_p_b[21]" LOC = G12;
#NET "fmc1_la_p_b[20]" LOC = F15;
#NET "fmc1_la_p_b[19]" LOC = G14;
#NET "fmc1_la_p_b[18]" LOC = J14;
#NET "fmc1_la_p_b[17]" LOC = B15;
#NET "fmc1_la_p_b[16]" LOC = F19;
#NET "fmc1_la_p_b[15]" LOC = H16;
#NET "fmc1_la_p_b[14]" LOC = F17;
#NET "fmc1_la_p_b[13]" LOC = G18;
#NET "fmc1_la_p_b[12]" LOC = F21;
#NET "fmc1_la_p_b[11]" LOC = G20;
#NET "fmc1_la_p_b[10]" LOC = L21;
#NET "fmc1_la_p_b[9]" LOC = M20;
#NET "fmc1_la_p_b[8]" LOC = F23;
#NET "fmc1_la_p_b[7]" LOC = G22;
#NET "fmc1_la_p_b[6]" LOC = B25;
#NET "fmc1_la_p_b[5]" LOC = M19;
#NET "fmc1_la_p_b[4]" LOC = D24;
#NET "fmc1_la_p_b[3]" LOC = E25;
#NET "fmc1_la_p_b[2]" LOC = J22;
#NET "fmc1_la_p_b[1]" LOC = H21;
#NET "fmc1_la_p_b[0]" LOC = C16;
#NET "fmc1_la_n_b[33]" LOC = H12;
#NET "fmc1_la_n_b[32]" LOC = G11;
#NET "fmc1_la_n_b[31]" LOC = K11;
#NET "fmc1_la_n_b[30]" LOC = H13;
#NET "fmc1_la_n_b[29]" LOC = E9;
#NET "fmc1_la_n_b[28]" LOC = K12;
#NET "fmc1_la_n_b[27]" LOC = L13;
#NET "fmc1_la_n_b[26]" LOC = K14;
#NET "fmc1_la_n_b[25]" LOC = E11;
#NET "fmc1_la_n_b[24]" LOC = F10;
#NET "fmc1_la_n_b[23]" LOC = K15;
#NET "fmc1_la_n_b[22]" LOC = E13;
#NET "fmc1_la_n_b[21]" LOC = F12;
#NET "fmc1_la_n_b[20]" LOC = E15;
#NET "fmc1_la_n_b[19]" LOC = F14;
#NET "fmc1_la_n_b[18]" LOC = H14;
#NET "fmc1_la_n_b[17]" LOC = A15;
#NET "fmc1_la_n_b[16]" LOC = E19;
#NET "fmc1_la_n_b[15]" LOC = G16;
#NET "fmc1_la_n_b[14]" LOC = E17;
#NET "fmc1_la_n_b[13]" LOC = F18;
#NET "fmc1_la_n_b[12]" LOC = E21;
#NET "fmc1_la_n_b[11]" LOC = F20;
#NET "fmc1_la_n_b[10]" LOC = K21;
#NET "fmc1_la_n_b[9]" LOC = L20;
#NET "fmc1_la_n_b[8]" LOC = E23;
#NET "fmc1_la_n_b[7]" LOC = F22;
#NET "fmc1_la_n_b[6]" LOC = A25;
#NET "fmc1_la_n_b[5]" LOC = L19;
#NET "fmc1_la_n_b[4]" LOC = C24;
#NET "fmc1_la_n_b[3]" LOC = D25;
#NET "fmc1_la_n_b[2]" LOC = H22;
#NET "fmc1_la_n_b[1]" LOC = G21;
#NET "fmc1_la_n_b[0]" LOC = A16;
#----------------------------------------
# FMC slot 2
#----------------------------------------
#NET "fmc2_gbtclk0m2c_p_i" LOC = AG18;
#NET "fmc2_gbtclk0m2c_n_i" LOC = AH18;
#NET "fmc2_dp0m2c_p_i" LOC = AG20;
#NET "fmc2_dp0m2c_n_i" LOC = AH20;
#NET "fmc2_dp0c2m_p_o" LOC = AJ21;
#NET "fmc2_dp0c2m_n_o" LOC = AK21;
#NET "fmc2_pg_c2m_o" LOC = AD30;
NET "fmc2_prsntm2c_n_i" LOC = AE29;
#NET "fmc2_scl_o" LOC = W29;
#NET "fmc2_sda_b" LOC = V30;
#NET "fmc2_tck_o" LOC = AH30;
#NET "fmc2_tdi_i" LOC = AK29;
#NET "fmc2_tdo_o" LOC = AG29;
#NET "fmc2_tms_o" LOC = AJ29;
#########################################
# clk0m2c, clk1m2c and la0-la33 can be assigned automatically with ucfgen
#NET "fmc2_clk1m2c_p_i" LOC = AH16;
#NET "fmc2_clk1m2c_n_i" LOC = AK16;
#NET "fmc2_clk0m2c_p_i" LOC = AF16;
#NET "fmc2_clk0m2c_n_i" LOC = AG16;
#NET "fmc2_la_p_b[33]" LOC = AA19;
#NET "fmc2_la_p_b[32]" LOC = W19;
#NET "fmc2_la_p_b[31]" LOC = Y21;
#NET "fmc2_la_p_b[30]" LOC = W20;
#NET "fmc2_la_p_b[29]" LOC = AC24;
#NET "fmc2_la_p_b[28]" LOC = AA22;
#NET "fmc2_la_p_b[27]" LOC = AB20;
#NET "fmc2_la_p_b[26]" LOC = AC19;
#NET "fmc2_la_p_b[25]" LOC = AB17;
#NET "fmc2_la_p_b[24]" LOC = AB21;
#NET "fmc2_la_p_b[23]" LOC = AF25;
#NET "fmc2_la_p_b[22]" LOC = AE24;
#NET "fmc2_la_p_b[21]" LOC = AD22;
#NET "fmc2_la_p_b[20]" LOC = AE19;
#NET "fmc2_la_p_b[19]" LOC = AE23;
#NET "fmc2_la_p_b[18]" LOC = AE21;
#NET "fmc2_la_p_b[17]" LOC = AC16;
#NET "fmc2_la_p_b[16]" LOC = AB14;
#NET "fmc2_la_p_b[15]" LOC = Y17;
#NET "fmc2_la_p_b[14]" LOC = Y15;
#NET "fmc2_la_p_b[13]" LOC = AC15;
#NET "fmc2_la_p_b[12]" LOC = AE15;
#NET "fmc2_la_p_b[11]" LOC = Y16;
#NET "fmc2_la_p_b[10]" LOC = Y14;
#NET "fmc2_la_p_b[9]" LOC = W14;
#NET "fmc2_la_p_b[8]" LOC = AB12;
#NET "fmc2_la_p_b[7]" LOC = AD12;
#NET "fmc2_la_p_b[6]" LOC = AD10;
#NET "fmc2_la_p_b[5]" LOC = AE11;
#NET "fmc2_la_p_b[4]" LOC = AJ15;
#NET "fmc2_la_p_b[3]" LOC = AE13;
#NET "fmc2_la_p_b[2]" LOC = AC11;
#NET "fmc2_la_p_b[1]" LOC = AG8;
#NET "fmc2_la_p_b[0]" LOC = AJ17;
#NET "fmc2_la_n_b[33]" LOC = AB19;
#NET "fmc2_la_n_b[32]" LOC = Y19;
#NET "fmc2_la_n_b[31]" LOC = AA21;
#NET "fmc2_la_n_b[30]" LOC = Y20;
#NET "fmc2_la_n_b[29]" LOC = AD24;
#NET "fmc2_la_n_b[28]" LOC = AC22;
#NET "fmc2_la_n_b[27]" LOC = AC20;
#NET "fmc2_la_n_b[26]" LOC = AD19;
#NET "fmc2_la_n_b[25]" LOC = AD17;
#NET "fmc2_la_n_b[24]" LOC = AC21;
#NET "fmc2_la_n_b[23]" LOC = AG25;
#NET "fmc2_la_n_b[22]" LOC = AF24;
#NET "fmc2_la_n_b[21]" LOC = AE22;
#NET "fmc2_la_n_b[20]" LOC = AF19;
#NET "fmc2_la_n_b[19]" LOC = AF23;
#NET "fmc2_la_n_b[18]" LOC = AF21;
#NET "fmc2_la_n_b[17]" LOC = AD16;
#NET "fmc2_la_n_b[16]" LOC = AC14;
#NET "fmc2_la_n_b[15]" LOC = AA17;
#NET "fmc2_la_n_b[14]" LOC = AA15;
#NET "fmc2_la_n_b[13]" LOC = AD15;
#NET "fmc2_la_n_b[12]" LOC = AF15;
#NET "fmc2_la_n_b[11]" LOC = AB16;
#NET "fmc2_la_n_b[10]" LOC = AA14;
#NET "fmc2_la_n_b[9]" LOC = Y13;
#NET "fmc2_la_n_b[8]" LOC = AC12;
#NET "fmc2_la_n_b[7]" LOC = AE12;
#NET "fmc2_la_n_b[6]" LOC = AE10;
#NET "fmc2_la_n_b[5]" LOC = AF11;
#NET "fmc2_la_n_b[4]" LOC = AK15;
#NET "fmc2_la_n_b[3]" LOC = AF13;
#NET "fmc2_la_n_b[2]" LOC = AD11;
#NET "fmc2_la_n_b[1]" LOC = AH8;
#NET "fmc2_la_n_b[0]" LOC = AK17;
#----------------------------------------
# I2C EEPROM
#----------------------------------------
#NET "scl_afpga_o" LOC = AC29;
#NET "sda_afpga_b" LOC = AA30;
#----------------------------------------
# Front panel IO and LEDs
#----------------------------------------
NET "fp_gpio_b[1]" LOC = R30;
NET "fp_gpio_b[2]" LOC = T28;
NET "fp_gpio_b[3]" LOC = U29;
NET "fp_gpio_b[4]" LOC = V27;
NET "fpgpio1_a2b_o" LOC = R29;
NET "fpgpio2_a2b_o" LOC = T30;
NET "fpgpio34_a2b_o" LOC = V28;
NET "term_en_o[1]" LOC = AB1;
NET "term_en_o[2]" LOC = W5;
NET "term_en_o[3]" LOC = W4;
NET "term_en_o[4]" LOC = V4;
NET "fp_led_n_o[0]" LOC = AD27;
NET "fp_led_n_o[1]" LOC = AD26;
NET "fp_led_n_o[2]" LOC = AC28;
NET "fp_led_n_o[3]" LOC = AC27;
NET "fp_led_n_o[4]" LOC = AE27;
NET "fp_led_n_o[5]" LOC = AE30;
NET "fp_led_n_o[6]" LOC = AF28;
NET "fp_led_n_o[7]" LOC = AE28;
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "tempid_dq_b" LOC = AC30;
#----------------------------------------
# Debug LEDs
#----------------------------------------
NET "dbg_led_n_o[4]" LOC = U7;
NET "dbg_led_n_o[3]" LOC = AG1;
NET "dbg_led_n_o[2]" LOC = AF1;
NET "dbg_led_n_o[1]" LOC = R6;
#----------------------------------------
# Boot interface
#----------------------------------------
#NET "2v5_afpga_cclk" LOC = AJ26;
#NET "2v5_afpga_cso_b" LOC = AK6;
#NET "2v5_afpga_init_b" LOC = AJ6;
#NET "2v5_afpga_miso" LOC = AJ25;
#NET "2v5_afpga_mosi" LOC = AK25;
#NET "2v5_afpga_program" LOC = AB8;
#NET "afpga_done" LOC = AD25;
#NET "afpga_m0" LOC = AK26;
#NET "afpga_m1" LOC = AG24;
#----------------------------------------
# JTAG interface
#----------------------------------------
#NET "prog_tms" LOC = K25;
#NET "prog_tdi" LOC = J24;
#NET "prog_tck" LOC = H23;
#NET "prog_tdo" LOC = H25;
#===============================================================================
# IO Standard Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_sysreset_n_i" IOSTANDARD = "LVCMOS33";
#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_gap_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_d_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_d_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_a_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_a_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_d_b[0]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_a_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_clk_n_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_clk_p_i" IOSTANDARD = "LVCMOS33";
#NET "si57x_clk_n_i" IOSTANDARD = "LVCMOS33";
#NET "si57x_clk_p_i" IOSTANDARD = "LVCMOS33";
#NET "pll_2afpga_n_i" IOSTANDARD = "LVCMOS33";
#NET "pll_2afpga_p_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Switches and button
#----------------------------------------
#NET "pushbutton_i" IOSTANDARD = "LVCMOS33";
#NET "noga_i[0]" IOSTANDARD = "LVCMOS33";
#NET "noga_i[1]" IOSTANDARD = "LVCMOS33";
#NET "noga_i[2]" IOSTANDARD = "LVCMOS33";
#NET "noga_i[3]" IOSTANDARD = "LVCMOS33";
#NET "noga_i[4]" IOSTANDARD = "LVCMOS33";
#NET "switch_i[0]" IOSTANDARD = "LVCMOS33";
#NET "switch_i[1]" IOSTANDARD = "LVCMOS33";
#NET "usega_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Inter-FPGA lines
#----------------------------------------
#NET "rsvd_b[0]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[1]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[2]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[3]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[4]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[5]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[6]" IOSTANDARD = "LVCMOS33";
#NET "rsvd_b[7]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[4]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[3]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[2]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[1]" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i[0]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SFP slot
#----------------------------------------
#NET "wr_los_i" IOSTANDARD = "LVCMOS33";
#NET "wr_moddef0_i" IOSTANDARD = "LVCMOS33";
#NET "wr_moddef1_o" IOSTANDARD = "LVCMOS33";
#NET "wr_moddef2_b" IOSTANDARD = "LVCMOS33";
#NET "wr_rateselect_o" IOSTANDARD = "LVCMOS33";
#NET "wr_txdisable_o" IOSTANDARD = "LVCMOS33";
#NET "wr_txfault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock controls
#----------------------------------------
#NET "oe_si57x_o" IOSTANDARD = "LVCMOS33";
#NET "si57x_scl_o" IOSTANDARD = "LVCMOS33";
#NET "si57x_sda_b" IOSTANDARD = "LVCMOS33";
#NET "si57x_tune_o" IOSTANDARD = "LVCMOS33";
#NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
#NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
#NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
#NET "uart_rxd_o" IOSTANDARD = "LVCMOS33";
#NET "uart_txd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# USB (optional)
#----------------------------------------
#NET "usb_clkout_i" IOSTANDARD = "LVCMOS33";
#NET "usb_oe_n_o" IOSTANDARD = "LVCMOS33";
#NET "usb_rd_n_o" IOSTANDARD = "LVCMOS33";
#NET "usb_rxf_n_i" IOSTANDARD = "LVCMOS33";
#NET "usb_siwua_i" IOSTANDARD = "LVCMOS33";
#NET "usb_txe_n_i" IOSTANDARD = "LVCMOS33";
#NET "usb_wr_n_o" IOSTANDARD = "LVCMOS33";
#NET "usb_d_b[0]" IOSTANDARD = "LVCMOS33";
#NET "usb_d_b[1]" IOSTANDARD = "LVCMOS33";
#NET "usb_d_b[2]" IOSTANDARD = "LVCMOS33";
#NET "usb_d_b[3]" IOSTANDARD = "LVCMOS33";
#NET "usb_d_b[4]" IOSTANDARD = "LVCMOS33";
#NET "usb_d_b[5]" IOSTANDARD = "LVCMOS33";
#NET "usb_d_b[6]" IOSTANDARD = "LVCMOS33";
#NET "usb_d_b[7]" IOSTANDARD = "LVCMOS33";
#NET "io7_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# VME P2
#----------------------------------------
#NET "p2_data_p_b[19]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[18]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[17]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[16]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[15]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[14]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[13]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[12]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[11]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[10]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[9]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[8]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[7]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[6]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[5]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[4]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[3]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[2]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[1]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_p_b[0]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[19]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[18]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[17]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[16]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[15]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[14]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[13]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[12]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[11]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[10]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[9]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[8]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[7]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[6]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[5]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[4]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[3]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[2]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[1]" IOSTANDARD = "LVCMOS25";
#NET "p2_data_n_b[0]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DDR3 (bank 4)
#----------------------------------------
NET "ddr_zio_b" IOSTANDARD = "SSTL15_II";
NET "ddr_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[15]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[14]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[13]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[12]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[11]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[10]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[9]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[8]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[7]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[6]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[5]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[4]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[3]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[2]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[1]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[0]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[2]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[1]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[0]" IOSTANDARD = "SSTL15_II";
#NET "ddr_a_o[14]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[13]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[12]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[11]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[10]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[9]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[8]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[7]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[6]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[5]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[4]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[3]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[2]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[1]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[0]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# DDR3 (bank 5)
#----------------------------------------
NET "ddr_2_zio_b" IOSTANDARD = "SSTL15_II";
NET "ddr_2_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_2_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_2_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_2_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_2_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_2_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_2_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_2_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_2_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_2_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_2_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_2_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_2_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_2_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_2_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[15]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[14]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[13]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[12]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[11]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[10]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[9]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[8]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[7]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[6]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[5]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[4]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[3]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[2]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[1]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_dq_b[0]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_ba_o[2]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_ba_o[1]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_ba_o[0]" IOSTANDARD = "SSTL15_II";
#NET "ddr_2_a_o[14]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[13]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[12]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[11]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[10]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[9]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[8]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[7]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[6]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[5]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[4]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[3]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[2]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[1]" IOSTANDARD = "SSTL15_II";
NET "ddr_2_a_o[0]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# FMC slot 1
#----------------------------------------
#NET "fmc1_pg_c2m_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS25";
#NET "fmc1_scl_o" IOSTANDARD = "LVCMOS25";
#NET "fmc1_sda_b" IOSTANDARD = "LVCMOS25";
#NET "fmc1_tck_o" IOSTANDARD = "LVCMOS25";
#NET "fmc1_tdi_i" IOSTANDARD = "LVCMOS25";
#NET "fmc1_tdo_o" IOSTANDARD = "LVCMOS25";
#NET "fmc1_tms_o" IOSTANDARD = "LVCMOS25";
#########################################
# clk0m2c, clk1m2c and la0-la33 can be assigned automatically with ucfgen
#NET "fmc1_clk1m2c_p_i" IOSTANDARD = "LVCMOS25";
#NET "fmc1_clk1m2c_n_i" IOSTANDARD = "LVCMOS25";
#NET "fmc1_clk0m2c_p_i" IOSTANDARD = "LVCMOS25";
#NET "fmc1_clk0m2c_n_I" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[33]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[32]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[31]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[30]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[29]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[28]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[27]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[26]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[25]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[24]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[23]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[22]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[21]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[20]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[19]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[18]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[17]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[16]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[15]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[14]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[13]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[12]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[11]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[10]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[9]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[8]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[7]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[6]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[5]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[4]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[3]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[2]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[1]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_p_b[0]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[33]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[32]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[31]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[30]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[29]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[28]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[27]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[26]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[25]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[24]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[23]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[22]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[21]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[20]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[19]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[18]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[17]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[16]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[15]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[14]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[13]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[12]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[11]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[10]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[9]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[8]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[7]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[6]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[5]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[4]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[3]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[2]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[1]" IOSTANDARD = "LVCMOS25";
#NET "fmc1_la_n_b[0]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot 2
#----------------------------------------
#NET "fmc2_pg_c2m_o" IOSTANDARD = "LVCMOS25";
NET "fmc2_prsntm2c_n_i" IOSTANDARD = "LVCMOS25";
#NET "fmc2_scl_o" IOSTANDARD = "LVCMOS25";
#NET "fmc2_sda_b" IOSTANDARD = "LVCMOS25";
#NET "fmc2_tck_o" IOSTANDARD = "LVCMOS25";
#NET "fmc2_tdi_i" IOSTANDARD = "LVCMOS25";
#NET "fmc2_tdo_o" IOSTANDARD = "LVCMOS25";
#NET "fmc2_tms_o" IOSTANDARD = "LVCMOS25";
#########################################
# clk0m2c, clk1m2c and la0-la33 can be assigned automatically with ucfgen
#NET "fmc2_clk1m2c_p_i" IOSTANDARD = "LVCMOS25";
#NET "fmc2_clk1m2c_n_i" IOSTANDARD = "LVCMOS25";
#NET "fmc2_clk0m2c_p_i" IOSTANDARD = "LVCMOS25";
#NET "fmc2_clk0m2c_n_i" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[33]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[32]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[31]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[30]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[29]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[28]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[27]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[26]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[25]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[24]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[23]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[22]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[21]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[20]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[19]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[18]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[17]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[16]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[15]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[14]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[13]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[12]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[11]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[10]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[9]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[8]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[7]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[6]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[5]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[4]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[3]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[2]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[1]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_p_b[0]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[33]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[32]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[31]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[30]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[29]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[28]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[27]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[26]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[25]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[24]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[23]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[22]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[21]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[20]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[19]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[18]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[17]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[16]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[15]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[14]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[13]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[12]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[11]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[10]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[9]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[8]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[7]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[6]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[5]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[4]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[3]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[2]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[1]" IOSTANDARD = "LVCMOS25";
#NET "fmc2_la_n_b[0]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# I2C EEPROM
#----------------------------------------
#NET "scl_afpga_o" IOSTANDARD = "LVCMOS33";
#NET "sda_afpga_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel IO and LEDs
#----------------------------------------
NET "fp_gpio_b[1]" IOSTANDARD = "LVCMOS33";
NET "fp_gpio_b[2]" IOSTANDARD = "LVCMOS33";
NET "fp_gpio_b[3]" IOSTANDARD = "LVCMOS33";
NET "fp_gpio_b[4]" IOSTANDARD = "LVCMOS33";
NET "fpgpio1_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fpgpio2_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fpgpio34_a2b_o" IOSTANDARD = "LVCMOS33";
NET "term_en_o[1]" IOSTANDARD = "LVCMOS33";
NET "term_en_o[2]" IOSTANDARD = "LVCMOS33";
NET "term_en_o[3]" IOSTANDARD = "LVCMOS33";
NET "term_en_o[4]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[0]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "fp_led_n_o[7]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "tempid_dq_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Debug LEDs
#----------------------------------------
NET "dbg_led_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "dbg_led_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "dbg_led_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "dbg_led_n_o[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Boot interface
#----------------------------------------
#NET "2v5_afpga_cclk" IOSTANDARD = "LVCMOS25";
#NET "2v5_afpga_cso_b" IOSTANDARD = "LVCMOS25";
#NET "2v5_afpga_init_b" IOSTANDARD = "LVCMOS25";
#NET "2v5_afpga_miso" IOSTANDARD = "LVCMOS25";
#NET "2v5_afpga_mosi" IOSTANDARD = "LVCMOS25";
#NET "2v5_afpga_program" IOSTANDARD = "LVCMOS25";
#NET "afpga_done" IOSTANDARD = "LVCMOS25";
#NET "afpga_m0" IOSTANDARD = "LVCMOS25";
#NET "afpga_m1" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# JTAG interface
#----------------------------------------
#NET "prog_tms" IOSTANDARD = "LVCMOS33";
#NET "prog_tdi" IOSTANDARD = "LVCMOS33";
#NET "prog_tck" IOSTANDARD = "LVCMOS33";
#NET "prog_tdo" IOSTANDARD = "LVCMOS33";
#===============================================================================
# Timing Constraints
#===============================================================================
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i_grp";
TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i_grp" 50 ns HIGH 50%;
NET "cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_32b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_32b_32b.cmp_ddr3_ctrl/c4_pll_lock" TIG;
NET "cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_32b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_32b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
NET "cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_32b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_32b_32b.cmp_ddr3_ctrl/c5_pll_lock" TIG;
NET "cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_32b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_32b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#===============================================================================
# Automatic FMC pins assignment
#===============================================================================
# <ucfgen_start>
# <ucfgen_end>
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment