Skip to content

S
Simple VME FMC Carrier SVEC
Commit add3785a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

svec7: SFPGA top level test with final FPGA Pinout

parent d02d1f4a
Hide whitespace changes
Inline Side-by-side
Showing with 193 additions and 138 deletions
hdl/top/svec7_sfpga/svec7_sfpga_top.ucf
View file @ add3785a
......@@ -4,31 +4,106 @@
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = B1;
#NET "vme_rst_n_i" LOC = G6;
#NET "vme_retry_oe_o" LOC = D3;
#NET "vme_retry_n_o" LOC = D1;
NET "vme_lword_n_b" LOC = B3;
#NET "vme_iackout_n_o" LOC = E4;
#NET "vme_iackin_n_i" LOC = F6;
#NET "vme_iack_n_i" LOC = E3;
NET "vme_tms_i" LOC = C13;
NET "vme_tms_i" IOSTANDARD="LVCMOS33";
NET "vme_tck_i" LOC = B14;
NET "vme_tck_i" IOSTANDARD="LVCMOS33";
NET "vme_trst_i" LOC = A14;
NET "vme_trst_i" IOSTANDARD="LVCMOS33";
NET "vme_tdi_i" LOC = D11;
NET "vme_tdi_i" IOSTANDARD="LVCMOS33";
NET "vme_tdo_o" LOC = D12;
NET "vme_tdo_o" IOSTANDARD="LVCMOS33";
NET "vme_sysclk_i" LOC = H4;
NET "vme_sysclk_i" IOSTANDARD="LVCMOS33";
NET "vme_tdo_oe_o" LOC = F10;
NET "vme_tdo_oe_o" IOSTANDARD="LVCMOS33";
NET "pushbutton_i" LOC = A13;
NET "pushbutton_i" IOSTANDARD="LVCMOS33";
NET "vme_berr_r_i" LOC = T15;
NET "vme_berr_r_i" IOSTANDARD="LVCMOS15";
NET "vme_dtack_r_i" LOC = T14;
NET "vme_dtack_r_i" IOSTANDARD="LVCMOS15";
NET "vme_retry_r_i" LOC = T13;
NET "vme_retry_r_i" IOSTANDARD="LVCMOS15";
#IO standards
NET "vme_addr_oe_n_o" LOC = K5;
NET "vme_addr_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_data_oe_n_o" LOC = K6;
NET "vme_data_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_dtack_oe_o" LOC = C3;
NET "vme_dtack_oe_o" IOSTANDARD="LVCMOS33";
NET "vme_dtack_n_o" LOC = C2;
NET "vme_ds_n_i[1]" LOC = N9;
NET "vme_ds_n_i[0]" LOC = P9;
NET "vme_data_oe_n_o" LOC = K6;
NET "vme_dtack_n_o" IOSTANDARD="LVCMOS33";
NET "vme_retry_oe_o" LOC = D3;
NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33";
NET "vme_retry_n_o" LOC = D1;
NET "vme_retry_n_o" IOSTANDARD="LVCMOS33";
NET "vme_berr_o" LOC = C1;
NET "vme_berr_o" IOSTANDARD="LVCMOS33";
NET "vme_write_n_i" LOC = B1;
NET "vme_write_n_i" IOSTANDARD="LVCMOS33";
NET "vme_sysreset_n_i" LOC = G6;
NET "vme_sysreset_n_i" IOSTANDARD="LVCMOS33";
NET "vme_addr_dir_o" LOC = B2;
NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33";
NET "vme_data_dir_o" LOC = F4;
#NET "vme_berr_o" LOC = C1;
NET "vme_data_dir_o" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[1]" LOC = F3;
NET "vme_ds_n_i[0]" LOC = A2;
NET "vme_ds_n_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_lword_n_b" LOC = B3;
NET "vme_lword_n_b" IOSTANDARD="LVCMOS33";
NET "vme_iackout_n_o" LOC = E4;
NET "vme_iackout_n_o" IOSTANDARD="LVCMOS33";
NET "vme_iackin_n_i" LOC = F6;
NET "vme_iackin_n_i" IOSTANDARD="LVCMOS33";
NET "vme_iack_n_i" LOC = E3;
NET "vme_iack_n_i" IOSTANDARD="LVCMOS33";
NET "vme_as_n_i" LOC = F5;
NET "vme_addr_oe_n_o" LOC = K5;
NET "vme_addr_dir_o" LOC = B2;
#NET "vme_irq_n_o[6]" LOC = C11;
#NET "vme_irq_n_o[5]" LOC = C8;
#NET "vme_irq_n_o[4]" LOC = D8;
#NET "vme_irq_n_o[3]" LOC = C10;
#NET "vme_irq_n_o[2]" LOC = E10;
#NET "vme_irq_n_o[1]" LOC = E8;
#NET "vme_irq_n_o[0]" LOC = E7;
NET "vme_as_n_i" IOSTANDARD="LVCMOS33";
NET "vme_irq_o[7]" LOC = C11;
NET "vme_irq_o[6]" LOC = C8;
NET "vme_irq_o[5]" LOC = D8;
NET "vme_irq_o[4]" LOC = C10;
NET "vme_irq_o[3]" LOC = E10;
NET "vme_irq_o[2]" LOC = E8;
NET "vme_irq_o[1]" LOC = E7;
NET "vme_irq_o[7]" IOSTANDARD="LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD="LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD="LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD="LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD="LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD="LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD="LVCMOS33";
NET "vme_gap_i" LOC = A3;
NET "vme_ga_i[4]" LOC = A10;
NET "vme_ga_i[3]" LOC = B10;
......@@ -108,42 +183,35 @@ NET "vme_addr_b[1]" LOC = M4;
#----------------------------------------
# Application FPGA boot control
#----------------------------------------
NET "boot_clk_o" LOC = F14;
NET "boot_config_o" LOC = C15;
NET "boot_done_i" LOC = C16;
NET "boot_dout_o" LOC = F13;
NET "boot_status_i" LOC = E16;
NET "boot_clk_o" LOC = F9;
NET "boot_config_o" LOC = D9;
NET "boot_done_i" LOC = B12;
NET "boot_dout_o" LOC = A11;
NET "boot_status_i" LOC = A12;
NET "debugled_n_o[2]" LOC = P15;
NET "debugled_n_o[1]" LOC = L16;
#IO standards
NET "vme_write_n_i" IOSTANDARD="LVCMOS33";
#NET "vme_rst_n_i" IOSTANDARD="LVCMOS33";
#NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33";
#NET "vme_retry_n_o" IOSTANDARD="LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD="LVCMOS33";
#NET "vme_iackout_n_o" IOSTANDARD="LVCMOS33";
#NET "vme_iackin_n_i" IOSTANDARD="LVCMOS33";
#NET "vme_iack_n_i" IOSTANDARD="LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD="LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD="LVCMOS33";
#NET "vme_berr_o" IOSTANDARD="LVCMOS33";
NET "vme_as_n_i" IOSTANDARD="LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[6]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[5]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[4]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[3]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[2]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[1]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[0]" IOSTANDARD="LVCMOS33";
NET "vme_gap_i" IOSTANDARD="LVCMOS33";
NET "boot_clk_o" IOSTANDARD="LVCMOS33";
NET "boot_config_o" IOSTANDARD="LVCMOS33";
NET "boot_done_i" IOSTANDARD="LVCMOS33";
NET "boot_dout_o" IOSTANDARD="LVCMOS33";
NET "boot_status_i" IOSTANDARD="LVCMOS33";
NET "debugled_n_o[2]" IOSTANDARD="LVCMOS15";
NET "debugled_n_o[1]" IOSTANDARD="LVCMOS15";
NET "afpga_mode_ctrl_o[0]" LOC=F13;
NET "afpga_mode_ctrl_o[0]" IOSTANDARD=LVCMOS15;
NET "afpga_mode_ctrl_o[1]" LOC=F14;
NET "afpga_mode_ctrl_o[1]" IOSTANDARD=LVCMOS15;
NET "afpga_mode_ctrl_o[2]" LOC=C15;
NET "afpga_mode_ctrl_o[2]" IOSTANDARD=LVCMOS15;
NET "vme_ga_i[4]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD="LVCMOS33";
......@@ -219,91 +287,69 @@ NET "vme_addr_b[3]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Application FPGA boot control
#----------------------------------------
NET "boot_clk_o" IOSTANDARD="LVCMOS33";
NET "boot_config_o" IOSTANDARD="LVCMOS33";
NET "boot_done_i" IOSTANDARD="LVCMOS33";
NET "boot_dout_o" IOSTANDARD="LVCMOS33";
NET "boot_status_i" IOSTANDARD="LVCMOS33";
NET "debugled_n_o[2]" IOSTANDARD="LVCMOS33";
NET "debugled_n_o[1]" IOSTANDARD="LVCMOS33";
NET "spi_sclk_o" IOSTANDARD="LVCMOS33";
NET "spi_cs_n_o" IOSTANDARD="LVCMOS33";
NET "spi_mosi_o" IOSTANDARD="LVCMOS33";
NET "spi_miso_i" IOSTANDARD="LVCMOS33";
NET "spi_sclk_o" LOC = R11;
NET "spi_cs_n_o" LOC = T3;
NET "spi_mosi_o" LOC = T10;
NET "spi_miso_i" LOC = P10;
# Clocks/resets
NET "rst_n_i" LOC = E15;
NET "rst_n_i" LOC = G5;
NET "lclk_i" LOC = H5;
NET "rst_n_i" IOSTANDARD="LVCMOS33";
NET "lclk_i" IOSTANDARD="LVCMOS33";
NET "pll_ce_o" IOSTANDARD="LVCMOS33";
NET "pll_ce_o" LOC=G14;
NET "pll_ce_o" LOC=E11;
#NET "afpga_flash_sck_i" LOC=G16;
#NET "afpga_flash_mosi_i" LOC=H15;
#NET "afpga_flash_cs_n_i" LOC=H16;
#NET "afpga_flash_miso_o" LOC=J14;
NET "afpga_cso_b_o" LOC=M11;
NET "afpga_mosi_o" LOC=P9;
NET "afpga_miso_i" LOC=N9;
NET "afpga_cclk_o" LOC=P11;
#NET "afpga_flash_sck_i" IOSTANDARD=LVCMOS33;
#NET "afpga_flash_mosi_i" IOSTANDARD=LVCMOS33;
#NET "afpga_flash_cs_n_i" IOSTANDARD=LVCMOS33;
#NET "afpga_flash_miso_o" IOSTANDARD=LVCMOS33;
NET "afpga_cso_b_o" IOSTANDARD="LVCMOS33";
NET "afpga_mosi_o" IOSTANDARD="LVCMOS33";
NET "afpga_miso_i" IOSTANDARD="LVCMOS33";
NET "afpga_cclk_o" IOSTANDARD="LVCMOS33";
NET "afpga_clk_p_i" IOSTANDARD=LVDS_33;
NET "afpga_clk_p_i" LOC=J11;
NET "afpga_tx_o[0]" IOSTANDARD=LVCMOS33;
NET "afpga_tx_o[0]" LOC=G16; # rsvd0
NET "afpga_tx_o[0]" DRIVE=24;
NET "afpga_clk_p_i" IOSTANDARD=LVDS_25;
NET "afpga_clk_p_i" LOC=J14;
NET "afpga_tx_o[0]" IOSTANDARD=SSTL15_II;
NET "afpga_tx_o[0]" LOC=F15;
NET "afpga_tx_o[0]" SLEW=FAST;
NET "afpga_tx_o[1]" IOSTANDARD=LVCMOS33;
NET "afpga_tx_o[1]" LOC=H15; # rsvd1
NET "afpga_tx_o[1]" DRIVE=24;
NET "afpga_tx_o[1]" IOSTANDARD=SSTL15_II;
NET "afpga_tx_o[1]" LOC=F16;
NET "afpga_tx_o[1]" SLEW=FAST;
NET "afpga_tx_o[2]" IOSTANDARD=LVCMOS33;
NET "afpga_tx_o[2]" LOC=H16; # rsvd2
NET "afpga_tx_o[2]" DRIVE=24;
NET "afpga_tx_o[2]" IOSTANDARD=SSTL15_II;
NET "afpga_tx_o[2]" LOC=G14;
NET "afpga_tx_o[2]" SLEW=FAST;
NET "afpga_tx_o[3]" IOSTANDARD=LVCMOS33;
NET "afpga_tx_o[3]" LOC=J14; # rsvd3
NET "afpga_tx_o[3]" DRIVE=24;
NET "afpga_tx_o[3]" IOSTANDARD=SSTL15_II;
NET "afpga_tx_o[3]" LOC=G16;
NET "afpga_tx_o[3]" SLEW=FAST;
NET "afpga_tx_o[4]" IOSTANDARD=LVCMOS33;
NET "afpga_tx_o[4]" LOC=J16; # rsvd4
NET "afpga_tx_o[4]" DRIVE=24;
NET "afpga_tx_o[4]" IOSTANDARD=SSTL15_II;
NET "afpga_tx_o[4]" LOC=H15;
NET "afpga_tx_o[4]" SLEW=FAST;
NET "afpga_rx_i[0]" IOSTANDARD=LVCMOS33;
NET "afpga_rx_i[0]" LOC=K15; # rsvd5
NET "afpga_rx_i[1]" IOSTANDARD=LVCMOS33;
NET "afpga_rx_i[1]" LOC=K16; # rsvd6
NET "afpga_rx_i[2]" IOSTANDARD=LVCMOS33;
NET "afpga_rx_i[2]" LOC=M15; # rsvd7
NET "afpga_rx_i[3]" IOSTANDARD=LVCMOS33;
NET "afpga_rx_i[3]" LOC=E13; # noga0
NET "afpga_rx_i[4]" IOSTANDARD=LVCMOS33;
NET "afpga_rx_i[4]" LOC=E12; # noga1
NET "vme_iackout_n_o" IOSTANDARD=LVCMOS33;
NET "vme_berr_o" IOSTANDARD=LVCMOS33;
NET "vme_retry_n_o" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[7]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[6]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[5]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[4]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[3]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[2]" IOSTANDARD=LVCMOS33;
NET "vme_irq_o[1]" IOSTANDARD=LVCMOS33;
NET "vme_retry_oe_o" IOSTANDARD=LVCMOS33;
NET "afpga_rx_i[0]" IOSTANDARD=SSTL15_II;
NET "afpga_rx_i[0]" LOC=H16; # rsvd5
NET "afpga_rx_i[1]" IOSTANDARD=SSTL15_II;
NET "afpga_rx_i[1]" LOC=G12; # rsvd6
NET "afpga_rx_i[2]" IOSTANDARD=SSTL15_II;
NET "afpga_rx_i[2]" LOC=H11; # rsvd7
NET "afpga_rx_i[3]" IOSTANDARD=SSTL15_II;
NET "afpga_rx_i[3]" LOC=H13; # noga0
NET "afpga_rx_i[4]" IOSTANDARD=SSTL15_II;
NET "afpga_rx_i[4]" LOC=H14; # noga1
#Created by Constraints Editor (xc6slx9-ftg256-2) - 2019/11/28
NET "lclk_i" TNM_NET = lclk_i;
TIMESPEC TS_lclk_i = PERIOD "lclk_i" 50 ns HIGH 50%;
NET "spi_cs_n_o" LOC=T3;
NET "spi_cs_n_o" IOSTANDARD=LVCMOS33;
NET "spi_miso_i" LOC=P10;
NET "spi_miso_i" IOSTANDARD=LVCMOS33;
NET "spi_mosi_o" LOC=T10;
NET "spi_mosi_o" IOSTANDARD=LVCMOS33;
NET "spi_sclk_o" LOC=R11;
NET "spi_sclk_o" IOSTANDARD=LVCMOS33;
hdl/top/svec7_sfpga/svec7_sfpga_top.vhd
View file @ add3785a
......@@ -64,6 +64,7 @@ entity svec7_sfpga_top is
-------------------------------------------------------------------------
vme_write_n_i : in std_logic;
vme_sysclk_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
......@@ -87,16 +88,31 @@ entity svec7_sfpga_top is
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
vme_noga_i : in std_logic_vector(4 downto 0);
vme_use_ga_i : in std_logic;
vme_berr_r_i : in std_logic;
vme_dtack_r_i : in std_logic;
vme_retry_r_i : in std_logic;
vme_trst_i : in std_logic;
vme_tck_i : in std_logic;
vme_tdi_i : in std_logic;
vme_tms_i : in std_logic;
vme_tdo_o : out std_logic;
vme_tdo_oe_o : out std_logic;
afpga_clk_p_i : in std_logic;
afpga_clk_n_i : in std_logic;
afpga_rx_i : in std_logic_vector(4 downto 0);
afpga_tx_o : out std_logic_vector(4 downto 0);
afpga_cso_b_o : out std_logic;
afpga_mosi_o : out std_logic;
afpga_miso_i : in std_logic;
afpga_cclk_o : out std_logic;
pushbutton_i :in std_logic;
-------------------------------------------------------------------------
-- AFPGA boot signals
-------------------------------------------------------------------------
......@@ -118,15 +134,8 @@ entity svec7_sfpga_top is
debugled_n_o : out std_logic_vector(2 downto 1);
-------------------------------------------------------------------------
-- Slave SPI interface allowing the Application FPGA to access the SPI flash
-------------------------------------------------------------------------
-- afpga_flash_sck_i : in std_logic;
-- afpga_flash_mosi_i : in std_logic;
-- afpga_flash_cs_n_i : in std_logic;
-- afpga_flash_miso_o : out std_logic;
afpga_mode_ctrl_o : out std_logic_vector(2 downto 0);
-- Onboard PLL enable signal. Must be one for the clock system to work.
pll_ce_o : out std_logic
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment