-------------------------------------------------------------------------------SVEC schematics review 24.04.2012replied by GK 27.04.2012replied back by CGS 27.04.2012-------------------------------------------------------------------------------MEETING SUMMARY + DATE 25.04.2012 15:30 - 16:30 + PLACE CERN Prevessin, Building 864, Room 1-A15 + SUBJECT SVEC Review + SVN http://svn.ohwr.org/svec/trunk/circuit_board/SVEC + REVISION 13 + PARTICIPANTS: Van der Bij, Erik EVB Erik.van.der.Bij@cern.ch Cattin, Matthieu MC matthieu.cattin@cern.ch Wlostowski, Tomasz TW tomasz.wlostowski@cern.ch Gil Soriano, Carlos CGS carlos.gil.soriano@cern.ch + SUMMARY There are still some errors from previous review: -+ SCHEMATICS Check out the USB interface and tidy up all the project. -+ LAYOUT Special attention should be taken to the SATA connector cutouts. Tidy up needed.=============================================================================== | ! : fatal | | + : important | | - : minor | | ? : question | | * : note | | A : already | ==============================================================================================================================================================SCHEMATICS+ SVEC_TOP.SchDoc--+ AFPGA.SchDoc--+ AFPGA_power.SchDoc--+ DDR3.SchDoc--+ DDR3_2.SchDoc--+ FPGA_GTP.SchDoc--+ JTAG Chain + SFPGA Flash.SchDoc--+ SFPGA.SchDoc--+ SFPGA_power.SchDoc--+ USB Interface.SchDoc--+ FMC_connectors.SchDoc--+ VME_Connectors.SchDoc--+ Front_panel.SchDoc--+ Power_supplies.SchDoc--+ Clk_generation.SchDoc--> BOM===============================================================================[!] EVERYTHING HERE STILL NEED BE CHANGED!!!!!--------------------------------------General:--------------------------------------[EVB] A- Frames should be recheck, still bad namingsfixed «CGS» There're still some pages referring to SPEC. Different names (some are Greg... others are G., revised by field is some pages in others not). Easy to check if check the schematics in printouts.[MC] A- Bad naming in the sheetsfixed «CGS» Still there are bad namings in sheet (check out Power supplies, it is writen down reference to SPEC project)[CGS] + The updated schematic PDF is missing. Generate and upload.it was in "files" section «CGS» True :), but delete the old one that is in the top of hierarchy.[CGS] + CERN logo missed in all the new sheets. Instead of using a text and then a rectangle, I would recommend a Text Frame with border set on (it automatically justifies).[CGS] + In general, CERN logos are not in the same position. Easiest check if schematics are print.----------------------------------------------------------------------------SVEC_TOP.SchDoc------------------------------------------------------------------------------------------------------------------AFPGA.SchDoc------------------------------------------------------------------------------------------------------------------Clk_generation.SchDoc--------------------------------------[MC] ? What is the comment box under IC12 (CDCM61004RHBT) for? Should be removedok, it wasjust to remind the IC settings «CGS» It should be removed.[TW] A+ 100 ohm resistors what for?it is part of Optional RC filter for 1-bit DAC from FPGA output.Can be used to fine tune Si571, which has a control voltage input. «CGS» If it is not mounted, please place the dashed rectangle on the top of it.----------------------------------------------------------------------------DDR3.SchDoc------------------------------------------------------------------------------------------------------------------DDR3_2.SchDoc------------------------------------------------------------------------------------------------------------------FPGA_GTP.SchDoc--------------------------------------[MC] - Use the same color for the text like "SATA connector", "Staight"... (c.f. FMC_connector.SchDoc).ok «CGS» Still strange colours in nets (PCIe_TXI_P, for instance).----------------------------------------------------------------------------JTAG Chain + SFPGA Flash.SchDoc------------------------------------------------------------------------------------------------------------------SFPGA.SchDoc----------------------------------[MC] - License frame is shifted compared to the text.fixed----------------------------------------------------------------------------USB Interface.SchDoc--------------------------------------[MC] ! IC17 power supplies are badly connected. VIO must be connected to P3V3. GND and EP must be connected to GND.that's true, no idea why the pins were shifted. «CGS» If it is not mounted, please place the dashed rectangle on the top of it.----------------------------------------------------------------------------FMC_connectors.SchDoc------------------------------------------------------------------------------------------------------------------VME_Connectors.SchDoc--------------------------------------[EVB] ! Remove JTAG lines. Are they used?no idea, they were connected in VFC board so I simply left them.[CGS] ! Buffers page is too crowded. Maybe it is better to split into VME DATA buffers and ADDRESS buffers (and put the rest whenever you consider better).----------------------------------------------------------------------------Front_panel.SchDoc--------------------------------------[MC] - Wires color of the ESD discharge circuit is different.you have got very good sight:) «CGS» Some parts are not mounted, please place the dashed rectangle on the top of it.----------------------------------------------------------------------------Power_supplies.SchDoc--------------------------------------[CGS] * Frame has SPEC title.----------------------------------------------------------------------------BOM--------------------------------------[CGS] ? R232 is the only 12K resistor. Can it be replaced and removed from BOM?well it must be 1% value required by the manufacturer of the FTDI chip. It is not mounted by default anyway «CGS» This part is not mounted, please put the 'No' mounted comment in the schematics. Some parts are not mounted, please place the dashed rectangle on the top of it.--------------------------------------===============================================================================LAYOUT===============================================================================[CGS] DRC not passed. Three errors of trace to trace spacing in FPGA. See attached document.[MC] + A few DDR traces on the bottom are still crossing the plane on L9.ok, fixed «CGS» Still DDR_DQ5/4 are crossing[MC] - P1V5 polygon doesn't have to go that far down on L9.it needs - the LVDS lines like ot have continous planes aroundhere we don't gain anything having it smalled «CGS» Indeed IC8 has some power nets connected with lines in top layer. Extended P1V5 plane to it and place some vias[MC] ! SATA connector cutout should be solved. Not possible to cut up there.why? Of course I can shift it to the edge or make bigger cutout, but there would be difficulty in installing it in the VME crate.I would simply leave it as it is and when stand-alone operation is needed, simply cut the PCB as is marked on the top overlay. removed the copper to make it easier. «EVB» Leave it as it is now and further one we can think of a better solution.[CGS] + Check Bottom overlay for FTG6 (upper part of the board ;-) ).
Erik van der Bij