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# Review01022012
# SVEC schematics review 01-02-2012
Present: Matthieu Cattin, Erik van der Bij, Tom Wlostowski, Carlos Gil
Soriano
\---
## Major (Design changes)
General
- The BOM must be seriously reduced\! The 'simple' SVEC has now even
many more capacitor and resistor types than the VFC.
- Remove 1nF and 10nF used for decoupling. Can be replaced by 100nF.
Even if 1nF and 10nF are needed in critical places (PLL filter), do
not use these values in decoupling.
JTAG\&CONFIG.SchDoc
- The board mustn't contain any jumper, it will reduce the number of
mistakes and questions.
- The FMC JTAG chain must be connected to the AFPGA (as on the SPEC).
- The JTAG chain with the connector (optionnaly the USB chip) must
only contains the 2 FPGAs.
- The AFPGA boot process must be simplified as follow:
- Only one big Flash is connected to the SFPGA.
- The AFPGA boot mode is always "Slave SPI" and the serial
progammation interface is connected to the SFPGA.
- The SFPGA is in charge of booting the AFPGA.
- The muxes can be removed, as well as one of the flash and the
"BOOT\_SEL" lines.
- The EEPROM connected to the SFPGA can be removed.
FmcConnector.SchDoc
- Add more decoupling capacitors.
VmeConnector.SchDoc
- Remove all BI power rails (V15N0BI, V5N2BI, V2N0BI, V5P0BI,
V15P0BI).
PowerSupplies.SchDoc
- The power distribution must be re-designed as follow:
- Use 3.3V from VME.
- Use one TPS52126 DC/DC to generate 1.2V and 2.5V from VME 5V.
- Use one TPS52126 DC/DC to generate 1.5V from VME 5V.
It can be placed close to the DDR chips as they're the only one
using 1.5V
\-\> OR use three single DC/DC to generate 1.2V, 1.5V and
2.5V.
In any cases use the same DC/DC type to reduce the BOM.
- The VME 12V is only used for the FMC slot.
- Use a big Molex connector (c.f. for standard PC motherboard) to
provide 12V, 5V and 3.3V in stand-alone.
- LEDs on all voltage rails should be removed, only one LED to
indicate that the board is powered is enough.
- If possible, use only one inductor type.
- C24 and C41 are rated 6.3V but connected to 12V\!\!
- If possible, use only one fuse type.
USB.SchDoc
- Remove the FT2232 chip.
- Replace the CP2102 by a CP2103 and use the GPIO pins for the JTAG
emulation.
SFPGA.SchDoc
- The DIP swithes can be removed. Not useful in a VME64x system.
- Move FMC I2C buses, FMC JTAG, FMC PGM2C, FMC Prsnt to AFPGA.
- Move temp. sensor and PCB revision resistor to AFPGA.
- Four or five PCB revision resistors are enough.
AFPGA\_power.SchDoc
- Component for encription should be "not mounted" by default.
- 1nF decoupling capacitors should be removed.
ClkGeneration.SchDoc
- Use the 20MHz VCXO for the SFPGA clock.
- PLL\_FMC2\_2P2 and L\_FPGA\_CLK are sharing the same divider in the
AD9516. Is that correct?
- What is PLL\_REF1 for?
FrontPannel.SchDoc
- Remove 51ohm serial termination resistors.
- Add MOSFET to enable the 50ohm parallel terminations.
If the LEMO is used as an output, we don't want is to be terminated
at the source.
-----
## Minor (Readability)
General
- OHR project is called SVEC, Altium project SVFC, top schematics
VMEFMC.
- SVEC should be used everywhere to avoid confusion.
- Add the OHL license text on all sheets. Copy this text block from
the SPEC schematics
- Use only A3 size for the schematics sheets. The 'top' sheet probably
won't fit on an A3, so keep it A2.
- Use the same naming convention for the active low signals (\#, \_N,
n, N). Notation with "\_N" suffix is prefered.
- Sheet numbering is not up-to-date, several sheets have the same
number.
- Use the same naming convention for the schematics files (e.g. all in
lower case).
- The top level sheet should contain "top" in the file name.
- Avoid leaving big empty space on a sheet.
VMEFMC.SchDoc
- Add names on the blocks.
- Indentation of the comment block is screwed and makes it hard to
read.
- Line crossing other blocks (P2\_DATA).
- Group pins per inteface and add interface description on the block
(as text).
- Consider using harness (e.g VME bus).
JTAG\&CONFIG.SchDoc
- The SFPGA boot mode is always "Master SPI", the comment should be
updated.
FmcConnector.SchDoc
- Remove "LVSD high speed" comments.
- Replace "LaP and LaN are LVSD lines" comments by something more
generic, like "LaP and LaN are 100ohms diff. pairs".
- Add "FMC Slot 1" and "FMC Slot 2" comments.
VmeConnector.SchDoc
- "LVDS pairs" comment should be more generic, like "100ohms diff.
pairs".
- Use arrow symbol for voltage rails (as on PowerSupplies sheet).
- Change V12P0VME to P12V\_VME.
- Change V12N0VME to M12V\_VME.
- Change V5P0VME to P5V\_VME.
- Change V5P0STDBYVME to P5V\_STDBY\_VME.
- Add "\_N" to active low signals.
DDR3.SchDoc
- DDR\_CAS and DDR\_RAS are active low signals, add "\_N".
DDR3\_2.SchDoc
- DDR\_2\_CAS and DDR\_2\_RAS are active low signals, add "\_N".
AFPGA.SchDoc
- Add bank supply voltage as a comment next to each block.
- Some port symbols are too small.
- Uniformise the net names (e.g. all in upper case).
fpga\_gtp.SchDoc
- The sheet template doesn't fit the sheet size, the title block is in
the middle of the page.
USB.SchDoc
- The sheet template doesn't fit the sheet size, the title block is in
the middle of the page.
SFPGA.SchDoc
- Add bank supply voltage as a comment next to each block.
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