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Created with Raphaël 2.2.08Feb5325Jan26Nov243227Oct26222115Sep113Jun20May14128621Apr1514910Mar317Feb1215Jan19Dec16131211227Nov1418Oct171526Sep2524231123Aug22225Jul242322191822Mar616Nov1030Oct131229Sep281823Feb19Mar26Nov15Aug2Apr6Mar7Feb4324Jan162Sep8Feb28Jan251429Nov1224Oct17213Sep20Jul1921Jun201512118Merge branch 'release/v2.0.1' into masterv2.0.1v2.0.1update changelogsw: get version compatibility from gitAdd data pages for DMA (so that it supports MBLT).svec_base_wr.vhd: add a workaround for planAheadMerge branch 'feature/dma-page' into developvme16_test: use pipelined wb, fix memmap commenttgingold-testcardtgingold-testcardsvec_vme16.vhd: set irq level and vectorvme64x_sim_pkg: export more read and write procedures.vmecore_test: add reload countervmecore_test: add interrupt status.vmecore_test: rewire the interrupt line.vmedma.c: add repeat and pattern options.vmecore_test: modify tb for 2esstvme64x_sim_pkg: add read for 2esstvmespy.c: add default action.vmedma.c: add --verbose, disp data in BE32.Add a testbench for the vmecore_test board.svec golden: add code to test DMA.golden: be more verbose of in case error on genbuild.golden_wr: adjust after renaming of template to base.tester_wr: add fpga-dev-idAdd tester_wr design (board to test irq).vmespy: add 2e-vmevmecore_test: cleanup and update.svec_base_common: adjust regexp for synchronizers.software: update test_vme, add vmedma and vmespy.Add vmespy application.vmecore_test: fix write decoding address.svec_vme16: add syn project, modify design.vme16_test: Allow the use of Manifest.py as top-level.vme16_test: cleanup.Import of vmecore_test ad vme16_test.svec_vmecore_test_top: update comments for PLL.svec_vmecore_test_top: adjust after vme64x_pkg changes.test_vme.c: add show-func.vmecore_test: adjust to xvme64x_core changes.Update Manifest.py and vmecore_test after last change in vme64x_core.Always drive all unused WB slave_o outputs to groundCheck CYC as well as STB in a WB cycle