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Programming languages used in this repository

Measured in bytes of code. Excludes generated and vendored code.

PercentageUsed programming language010203040506070VHDLCPythonSystemVerilogMakefile

Commit statistics for 388c3816007d54e246faebfde877b146416312ed Jun 08 - Jan 16

Excluding merge commits. Limited to 2,000 commits.
Switch branch/tag
  • adam-tdc
  • feature/bootloader-retry
  • feature/svec-dbg-irq-gen
  • feature/svec-dma
  • master default protected
  • proposed_master protected
  • tgingold-testcard
  • tgingold-tester_wr
  • tom-ctrv-v5-bootloader
  • tom-ddmtd-clock-output
  • tom-svec7
  • tom-svec7-test
  • varodek_develop_svec
  • v3.1.0
  • v3.0.0
  • v2.0.4
  • v2.0.3
  • v2.0.2
  • v2.0.1
  • v1.5.2
  • v1.5.1
  • v1.5.0
  • v1.4.12
  • v1.4.11
  • v1.4.10
  • v1.4.9
  • v1.4.8
  • v1.4.7
  • v1.4.6
  • v1.4.5
  • v1.4.4
  • v1.4.3
  • v1.4.2
33 results
  • Total: 42 commits
  • Average per day: 0.1 commits
  • Authors: 2

Commits per day of month

No. of commitsDay of month0246812345678910111213141516171819202122232425262728293031

Commits per weekday

No. of commitsWeekday03691215SundayMondayTuesdayWednesdayThursdayFridaySaturday

Commits per day hour (UTC)

No. of commitsHour (UTC)02468101201234567891011121314151617181920212223