Commits · proposed_master · Projects / Simple VME FMC Carrier SVEC · GitLab

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Nov 14, 2019
- svec_vme16: add syn project, modify design. · 72f8d1dd
  Tristan Gingold authored 5 years ago
  
  72f8d1dd
- vme16_test: Allow the use of Manifest.py as top-level. · 6d427baa
  Tristan Gingold authored 5 years ago
  
  6d427baa
- vme16_test: cleanup. · a8044e02
  Tristan Gingold authored 5 years ago
  
  a8044e02
- Import of vmecore_test ad vme16_test. · eacd04d6
  Tristan Gingold authored 5 years ago
  
  eacd04d6
Sep 24, 2019
- Update golden after renaming. · 4b432b68
  Tristan Gingold authored 5 years ago
  
  4b432b68
Sep 23, 2019
- Rename template -> base · 46bd7e78
  Tristan Gingold authored 5 years ago
  
  46bd7e78
Aug 22, 2019
- svec golden wr: fix port names, connexions... Tested ok. · 3da89c5c
  Tristan Gingold authored 5 years ago
  
  3da89c5c
- svec template: fix interrupt wiring. · bcf5473e
  Tristan Gingold authored 5 years ago
  
  bcf5473e
Aug 02, 2019
- [hdl] move UCFs to syn/common restructure DDR constraints · d8f4adcc
  Dimitris Lampridis authored 5 years ago
  
  d8f4adcc
- [hdl] relax DMTD phase constraint · 53203b3c
  Dimitris Lampridis authored 5 years ago
  
  53203b3c
Jul 25, 2019
- [hdl] fix front-panel GPIO locations, they were inverted · 416aea5d
  Dimitris Lampridis authored 5 years ago
  
  416aea5d
- [hdl] rework cross-clock domain constraints · f5c8df30
  Dimitris Lampridis authored 5 years ago
  
  f5c8df30
- [hdl] move DDR constraints to their dedicated UCF files · badab820
  Dimitris Lampridis authored 5 years ago
  
  badab820
- [doc] add clk_20m_vcxo_i LOC constraints · 6cb80a43
  Dimitris Lampridis authored 5 years ago
  
  6cb80a43
- [hdl] drive SPI outputs to zero when g_WITH_SPI is not set · 28935e4f
  Dimitris Lampridis authored 5 years ago
  
  28935e4f
- testbench: drives ddr4. · d9e35137
  Tristan Gingold authored 5 years ago
  
  d9e35137
- svec_template_wr: specify granularity of ddr4. · eed7920a
  Tristan Gingold authored 5 years ago
  
  eed7920a
Jul 24, 2019
- [hdl] add default values to DDR WB interfaces · 7e91ab32
  Dimitris Lampridis authored 5 years ago
  
  7e91ab32
- [hdl] expose external WR 10MHz clock and PPS inputs · 5a28f2c8
  Dimitris Lampridis authored 5 years ago
  
  5a28f2c8
- [hdl] expose WR aux clock interface · 0ea886c0
  Dimitris Lampridis authored 5 years ago
  
  0ea886c0
- Add testbench for template. · 1ed0766d
  Tristan Gingold authored 5 years ago
  
  1ed0766d
- svec template: use vme64x core in pipelined mode. · 06336586
  Tristan Gingold authored 5 years ago
  
  06336586
- Regenerate svec_template_regs. · 1ee43aec
  Tristan Gingold authored 5 years ago
  
  1ee43aec
- [hdl] add root Manifest · fe843b2b
  Dimitris Lampridis authored 5 years ago
  
  fe843b2b
- [hdl] update submodules to new OHWR and point to latest stable commits · 566559f0
  Dimitris Lampridis authored 5 years ago
  
  566559f0
Jul 23, 2019
- svec template: add ddr registers. · bbe9114e
  Tristan Gingold authored 5 years ago
  
  bbe9114e
Jul 22, 2019
- add golden_wr · a8d09a80
  Tristan Gingold authored 5 years ago
  
  a8d09a80
Jul 19, 2019
- Update svec template. · 7381dcab
  Tristan Gingold authored 5 years ago
  
  7381dcab
Jul 18, 2019
- Add initial version of svec template. · 7c4136db
  Tristan Gingold authored 5 years ago
  
  7c4136db
Sep 18, 2017
- remove unused project files · 481562e0
  Dimitris Lampridis authored 7 years ago
  
  481562e0
- golden: remove Xilinx ISE project file and introduce hdlmake Manifest.py for synthesis · 8e2745f6
  Dimitris Lampridis authored 7 years ago
```
sfpga_bootloader: remove Xilinx ISE project file and update hdlmake Manifest.py for synthesis

Solves #1642
```
  8e2745f6
- golden: add missing timing constraint for 20MHz VCXO clock input. Solves #1641. · cf49b099
  Dimitris Lampridis authored 7 years ago
  
  cf49b099
Mar 19, 2015
- vme-flasher: removed CERN specific makefile options · b3454979
  Tomasz Wlostowski authored 9 years ago
  
  b3454979
- software: removed obsolete sveclib · f6c7fa2c
  Tomasz Wlostowski authored 9 years ago
  
  f6c7fa2c
- vme-flasher: added loading bitstream to AFPGA mode without programming the flash · b72b6669
  Tomasz Wlostowski authored 9 years ago
  
  b72b6669
- svec-flasher: added support for direct FPGA booting · 7a6e1838
  Tomasz Wlostowski authored 9 years ago
  
  7a6e1838
Nov 26, 2014
- Updated documentation date · f2a7a4e0
  Tomasz Wlostowski authored 10 years ago
  
  f2a7a4e0
Aug 15, 2014
- svec-flasher: added update over VME option · 2368263a
  Tomasz Wlostowski authored 10 years ago
  
  2 tags
  
  2368263a
- sfpga_bootloader: provide SPI flash to AFPGA when the bootloader is done · f2768ddc
  Tomasz Wlostowski authored 10 years ago
  
  f2768ddc
Apr 02, 2014
- hdl/golden: updated manifest & ISE project · b2d7a10f
  Tomasz Wlostowski authored 10 years ago
  
  gateware-v2.0
  
  b2d7a10f