| ... | @@ -118,7 +118,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
... | @@ -118,7 +118,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- **1x tx-abscal**
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- **1x tx-abscal**
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- **10 MHz reference clock in/out**
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- **10 MHz reference clock in/out**
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- **PPS in/out**
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- **PPS in/out**
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- **1x GTX Tx/Rx (using 125 MHz reference clock; optional other when using Z035/Z045)**
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- **1x GTX Tx/Rx (using 125 MHz reference clock; optional other reference clock when using Z035/Z045)**
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- **1x spare**
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- **1x spare**
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- 1x connector for optional cooling fan
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- 1x connector for optional cooling fan
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- FPGA configuration. The FPGA can optionally be programmed from:
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- FPGA configuration. The FPGA can optionally be programmed from:
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| ... | @@ -210,5 +210,5 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
... | @@ -210,5 +210,5 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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-----
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-----
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12 June 2019
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18 June 2019
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