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@@ -76,7 +76,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
             max)
       - 1x 8 Gbit (1 GByte) DDR3 IC connected to the programmable logic
           - for bandwidth reasons
-          - Possibly a second 8 Gbit DDR3 IC to prevent the DDR3 problem
+          - possibly a second 8 Gbit DDR3 IC to prevent the DDR3 problem
             of the latency and turnaround from READ to WRITE – two banks
             solve the problem. 
       - 1x SPI **xx** Mbit flash PROM for multiboot FPGA powerup