| ... | ... | @@ -43,6 +43,8 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- Possibility to mount Z035: XC7Z035-1FBG676C or XC7Z045-1FBG676C
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- 8 GTX receivers (2 used for PCIe, 1 for SFP, 5 for FMC)
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- FMC slot with high pin count (HPC) connector
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- ***Under discussion. Possibly only GTX lines connected and Vadj
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fixed at 2.5V (23/10/18)***
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- Vadj programmable at 1.8V and 2.5V
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- 2.5V can only be used with a LPC FMC mezzanine: only the LPC
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pins (LA bank) are 2.5V tolerant.
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| ... | ... | @@ -58,8 +60,8 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- 1x Fixed frequency oscillator for Application processor unit
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(APU) (frequency?)
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- 1x 10-280 MHz VCXO controlled by I2C and a DAC with SPI
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interface. Starts up at 100 MHz (Silicon Labs Si571, freely
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usable)
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interface. Starts up at 100 MHz (Silicon Labs <s>Si571</s>
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***Si570 (23/10/18)***, freely usable)
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- 1x 125 MHz TCXO controlled by a DAC with SPI interface (used by
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[White Rabbit PTP
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core](https://www.ohwr.org/project/wr-cores/wikis/Wrpc-core))
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| ... | ... | @@ -223,5 +225,5 @@ Prototype available by end April 2019.</td> |
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-----
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17 September 2018
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23 October 2018
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