- 13 Aug, 2019 1 commit
-
-
Federico Vaga authored
Signed-off-by:Federico Vaga <federico.vaga@cern.ch>
-
- 12 Aug, 2019 7 commits
-
-
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by:
-
- 07 Aug, 2019 3 commits
-
-
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Like this we can see that the state machine started (we should see the BUSY bit set) Signed-off-by: -
Federico Vaga authored
The FPGA SPEC core is described using cheby. Generate the header file on build (it requires cheby) and include it. Signed-off-by:
-
- 06 Aug, 2019 6 commits
-
-
Federico Vaga authored
-
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
It is not understood why this is necessary, but it happens that without this delay, after programming the FPGA, the DDR status bit is not set yet. So, here we wait for the FPGA to calibrate the DDR. Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by:
-
- 02 Aug, 2019 2 commits
-
-
Dimitris Lampridis authored -
Tristan Gingold authored
-
- 01 Aug, 2019 3 commits
-
-
Federico Vaga authored
Signed-off-by: -
Tristan Gingold authored
-
Federico Vaga authored
Signed-off-by:
-
- 30 Jul, 2019 12 commits
-
-
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
Signed-off-by: -
Federico Vaga authored
While drivers are processing a level interrupts, the bit in GPIO_INT_STATUS get set and it sticks there. Only when drivers processed the level interrupts we are sure that the bit does not get set again. Therefore, only at this point we can properly clean the GPIO_INT_STATUS. Then we may have problems, with the edge interrupts, so we put them (edge interrupts) back in the GPIO_INT_STATUS. About this last point we are not sure that is going to work, but in all our installation we are not going to use edge interrupts because they are risky. Signed-off-by: -
Federico Vaga authored
The hardware does not keep in count the INT_MASK, but on our side we do no want to handle interrupts that have not been requested. Signed-off-by: -
Federico Vaga authored
Signed-off-by:
-
- 19 Jul, 2019 4 commits
-
-
Tristan Gingold authored
-
Federico Vaga authored
Signed-off-by: -
Tristan Gingold authored
-
Tristan Gingold authored
-
- 18 Jul, 2019 2 commits
-
-
Federico Vaga authored
It is not that useful to update the change log during development. I put in it information about previous development, before releaseing the version 1.4 (yes, we start with that number) we have to update this file. I choosed to keep it here and visible as a reminder of our duties Signed-off-by: -
Federico Vaga authored
Now that the project contains both HDL and software the README needs an update. I just wrote few lines here because the plan is to have a proper documentation in doc/. Signed-off-by:
-
