Commit 2647a65e authored by Federico Vaga's avatar Federico Vaga

sw:drv: add delay before checking DDR status

It is not understood why this is necessary, but it happens that
without this delay, after programming the FPGA, the DDR status bit is not
set yet. So, here we wait for the FPGA to calibrate the DDR.
Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent d2ddb8ac
......@@ -284,6 +284,7 @@ static int spec_fpga_dma_init(struct spec_fpga *spec_fpga)
if (!(spec_fpga->meta->cap & SPEC_META_CAP_DMA))
return 0;
mdelay(1);
ddr_status = ioread32(spec_fpga->fpga + SPEC_FPGA_CSR_DDR_STATUS);
if (!(ddr_status & SPEC_FPGA_CSR_DDR_STATUS_DONE)) {
dev_err(&spec_fpga->dev,
......
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