introduce golden_wr for SPEC 150T

7e5a0a9b · Dimitris Lampridis · 178d3493 · 7e5a0a9b · 7e5a0a9b · 7e5a0a9b
Commit 7e5a0a9b authored Jul 16, 2019 by Dimitris Lampridis
Showing with 70 additions and 0 deletions

.gitignore hdl/syn/golden_wr-150T/.gitignore +5 -0

Manifest.py hdl/syn/golden_wr-150T/Manifest.py +33 -0

syn_extra_steps.tcl hdl/syn/golden_wr-150T/syn_extra_steps.tcl +32 -0

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--- a/hdl/syn/golden_wr-150T/.gitignore
+++ b/hdl/syn/golden_wr-150T/.gitignore
+*
+!.gitignore
+!Manifest.py
+!*.ucf
+!syn_extra_steps.tcl
--- a/hdl/syn/golden_wr-150T/Manifest.py
+++ b/hdl/syn/golden_wr-150T/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../../ip_cores"
+
+syn_device = "xc6slx150t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_project = "spec_golden_wr.xise"
+syn_tool = "ise"
+syn_top = "spec_golden_wr"
+
+board = "spec"
+ctrls = ["bank3_64b_32b" ]
+
+modules = {
+  "local" : [
+      "../../top/golden_wr",
+      ],
+  "git" : [
+      "https://ohwr.org/project/wr-cores.git",
+      "https://ohwr.org/project/general-cores.git",
+      "https://ohwr.org/project/gn4124-core.git",
+      "https://ohwr.org/project/ddr3-sp6-core.git",
+  ],
+}
+
+syn_post_project_cmd = (
+    "$(TCL_INTERPRETER) " + \
+    fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
+    syn_tool + " $(PROJECT_FILE);" \
+    "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
+)
--- a/hdl/syn/golden_wr-150T/syn_extra_steps.tcl
+++ b/hdl/syn/golden_wr-150T/syn_extra_steps.tcl
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+xilinx::project save
+
+xilinx::project close