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Simple PCIe FMC carrier SPEC
Commit 178d3493 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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golden_wr: cleanup Manifest and add synthesis extra steps TCL script

parent b3ac19ae
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hdl/syn/golden_wr/.gitignore 0 → 100644
View file @ 178d3493
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/golden_wr/Manifest.py
View file @ 178d3493
......@@ -35,3 +35,5 @@ try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/golden_wr/syn_extra_steps.tcl 0 → 100644
View file @ 178d3493
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
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