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Simple PCIe FMC carrier SPEC
Commit 25a56b99 authored by Tristan Gingold's avatar Tristan Gingold
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Change template registers map.

parent 67ba287a
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Showing with 134 additions and 69 deletions
hdl/golden/top/spec_golden.ucf
View file @ 25a56b99
...@@ -193,7 +193,6 @@ NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25"; ...@@ -193,7 +193,6 @@ NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
#--------------------------------------------------------------------------------------------- #---------------------------------------------------------------------------------------------
# GN4124 # GN4124
NET "gn_rst_n" TIG; NET "gn_rst_n" TIG;
NET "inst_template/cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_clk_in/P_clk; NET "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
......
hdl/template/spec_template.vhd
View file @ 25a56b99
...@@ -106,6 +106,7 @@ ...@@ -106,6 +106,7 @@
signal genum_wb_out : t_wishbone_master_out; signal genum_wb_out : t_wishbone_master_out;
signal genum_wb_in : t_wishbone_master_in; signal genum_wb_in : t_wishbone_master_in;
signal gennum_status : std_logic_vector(31 downto 0);
signal metadata_addr : std_logic_vector(5 downto 2); signal metadata_addr : std_logic_vector(5 downto 2);
signal metadata_data : std_logic_vector(31 downto 0); signal metadata_data : std_logic_vector(31 downto 0);
...@@ -210,7 +211,7 @@ ...@@ -210,7 +211,7 @@
--------------------------------------------------------- ---------------------------------------------------------
-- Control and status -- Control and status
rst_n_a_i => gn_RST_N, rst_n_a_i => gn_RST_N,
status_o => open, status_o => gennum_status,
--------------------------------------------------------- ---------------------------------------------------------
-- P2L Direction -- P2L Direction
...@@ -265,6 +266,7 @@ ...@@ -265,6 +266,7 @@
--------------------------------------------------------- ---------------------------------------------------------
-- CSR wishbone interface (master pipelined) -- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys, csr_clk_i => clk_sys,
csr_rst_n_i => '1',
csr_adr_o => genum_wb_out.adr, csr_adr_o => genum_wb_out.adr,
csr_dat_o => genum_wb_out.dat, csr_dat_o => genum_wb_out.dat,
csr_sel_o => genum_wb_out.sel, csr_sel_o => genum_wb_out.sel,
...@@ -276,7 +278,6 @@ ...@@ -276,7 +278,6 @@
csr_stall_i => genum_wb_in.stall, csr_stall_i => genum_wb_in.stall,
csr_err_i => genum_wb_in.err, csr_err_i => genum_wb_in.err,
csr_rty_i => genum_wb_in.rty, csr_rty_i => genum_wb_in.rty,
csr_int_i => '0', -- Not used
--------------------------------------------------------- ---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master) -- L2P DMA Interface (Pipelined Wishbone master)
...@@ -285,8 +286,7 @@ ...@@ -285,8 +286,7 @@
dma_ack_i => '1', dma_ack_i => '1',
dma_stall_i => '0', dma_stall_i => '0',
dma_err_i => '0', dma_err_i => '0',
dma_rty_i => '0', dma_rty_i => '0');
dma_int_i => '0');
i_devs: entity work.spec_template_regs i_devs: entity work.spec_template_regs
port map ( port map (
...@@ -310,13 +310,17 @@ ...@@ -310,13 +310,17 @@
metadata_data_o => open, metadata_data_o => open,
-- offset to the application metadata -- offset to the application metadata
app_offset_i => x"0000_0000", csr_app_offset_i => x"0000_0000",
csr_resets_global_o => csr_rst_gbl, csr_resets_global_o => csr_rst_gbl,
csr_resets_appl_o => csr_rst_app, csr_resets_appl_o => csr_rst_app,
-- presence lines for the fmcs -- presence lines for the fmcs
csr_fmc_presence_i => fmc_presence, csr_fmc_presence_i => fmc_presence,
csr_gn4124_status_i => gennum_status,
csr_ddr_status_calib_done_i => '0',
csr_pcb_rev_rev_i => x"0",
-- Thermometer and unique id -- Thermometer and unique id
therm_id_i => therm_id_in, therm_id_i => therm_id_in,
therm_id_o => therm_id_out, therm_id_o => therm_id_out,
......
hdl/template/spec_template_regs.cheby
View file @ 25a56b99
...@@ -8,23 +8,16 @@ memory-map: ...@@ -8,23 +8,16 @@ memory-map:
description: a ROM containing the carrier metadata description: a ROM containing the carrier metadata
size: 0x40 size: 0x40
interface: sram interface: sram
- reg:
address: 0x40
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- submap:
name: therm_id
description: Thermometer and unique id
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- block: - block:
name: csr name: csr
description: carrier and fmc status and control description: carrier and fmc status and control
address: 0x40
children: children:
- reg:
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- reg: - reg:
name: resets name: resets
description: global and application resets description: global and application resets
...@@ -42,6 +35,38 @@ memory-map: ...@@ -42,6 +35,38 @@ memory-map:
description: presence lines for the fmcs description: presence lines for the fmcs
access: ro access: ro
width: 32 width: 32
- reg:
name: gn4124_status
description: status of gennum
access: ro
width: 32
- reg:
name: ddr_status
description: status of the ddr3 controller
access: ro
width: 32
children:
- field:
description: Set when calibration is done.
name: calib_done
range: 0
- reg:
name: pcb_rev
description: pcb revision
access: ro
width: 32
children:
- field:
name: rev
range: 3-0
- submap:
name: therm_id
description: Thermometer and unique id
address: 0x70
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- submap: - submap:
name: fmc_i2c name: fmc_i2c
description: i2c controllers to the fmcs description: i2c controllers to the fmcs
......
hdl/template/spec_template_regs.vhd
View file @ 25a56b99
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