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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
25a56b99
Commit
25a56b99
authored
Jul 10, 2019
by
Tristan Gingold
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Plain Diff
Change template registers map.
parent
67ba287a
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4 changed files
with
134 additions
and
69 deletions
+134
-69
spec_golden.ucf
hdl/golden/top/spec_golden.ucf
+0
-1
spec_template.vhd
hdl/template/spec_template.vhd
+9
-5
spec_template_regs.cheby
hdl/template/spec_template_regs.cheby
+38
-13
spec_template_regs.vhd
hdl/template/spec_template_regs.vhd
+87
-50
No files found.
hdl/golden/top/spec_golden.ucf
View file @
25a56b99
...
...
@@ -193,7 +193,6 @@ NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
#---------------------------------------------------------------------------------------------
# GN4124
NET "gn_rst_n" TIG;
NET "inst_template/cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
...
...
hdl/template/spec_template.vhd
View file @
25a56b99
...
...
@@ -106,6 +106,7 @@
signal
genum_wb_out
:
t_wishbone_master_out
;
signal
genum_wb_in
:
t_wishbone_master_in
;
signal
gennum_status
:
std_logic_vector
(
31
downto
0
);
signal
metadata_addr
:
std_logic_vector
(
5
downto
2
);
signal
metadata_data
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -210,7 +211,7 @@
---------------------------------------------------------
-- Control and status
rst_n_a_i
=>
gn_RST_N
,
status_o
=>
open
,
status_o
=>
gennum_status
,
---------------------------------------------------------
-- P2L Direction
...
...
@@ -265,6 +266,7 @@
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i
=>
clk_sys
,
csr_rst_n_i
=>
'1'
,
csr_adr_o
=>
genum_wb_out
.
adr
,
csr_dat_o
=>
genum_wb_out
.
dat
,
csr_sel_o
=>
genum_wb_out
.
sel
,
...
...
@@ -276,7 +278,6 @@
csr_stall_i
=>
genum_wb_in
.
stall
,
csr_err_i
=>
genum_wb_in
.
err
,
csr_rty_i
=>
genum_wb_in
.
rty
,
csr_int_i
=>
'0'
,
-- Not used
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
...
...
@@ -285,8 +286,7 @@
dma_ack_i
=>
'1'
,
dma_stall_i
=>
'0'
,
dma_err_i
=>
'0'
,
dma_rty_i
=>
'0'
,
dma_int_i
=>
'0'
);
dma_rty_i
=>
'0'
);
i_devs
:
entity
work
.
spec_template_regs
port
map
(
...
...
@@ -310,13 +310,17 @@
metadata_data_o
=>
open
,
-- offset to the application metadata
app_offset_i
=>
x"0000_0000"
,
csr_app_offset_i
=>
x"0000_0000"
,
csr_resets_global_o
=>
csr_rst_gbl
,
csr_resets_appl_o
=>
csr_rst_app
,
-- presence lines for the fmcs
csr_fmc_presence_i
=>
fmc_presence
,
csr_gn4124_status_i
=>
gennum_status
,
csr_ddr_status_calib_done_i
=>
'0'
,
csr_pcb_rev_rev_i
=>
x"0"
,
-- Thermometer and unique id
therm_id_i
=>
therm_id_in
,
therm_id_o
=>
therm_id_out
,
...
...
hdl/template/spec_template_regs.cheby
View file @
25a56b99
...
...
@@ -8,23 +8,16 @@ memory-map:
description: a ROM containing the carrier metadata
size: 0x40
interface: sram
- reg:
address: 0x40
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- submap:
name: therm_id
description: Thermometer and unique id
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- block:
name: csr
description: carrier and fmc status and control
address: 0x40
children:
- reg:
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- reg:
name: resets
description: global and application resets
...
...
@@ -42,6 +35,38 @@ memory-map:
description: presence lines for the fmcs
access: ro
width: 32
- reg:
name: gn4124_status
description: status of gennum
access: ro
width: 32
- reg:
name: ddr_status
description: status of the ddr3 controller
access: ro
width: 32
children:
- field:
description: Set when calibration is done.
name: calib_done
range: 0
- reg:
name: pcb_rev
description: pcb revision
access: ro
width: 32
children:
- field:
name: rev
range: 3-0
- submap:
name: therm_id
description: Thermometer and unique id
address: 0x70
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fmc_i2c
description: i2c controllers to the fmcs
...
...
hdl/template/spec_template_regs.vhd
View file @
25a56b99
-- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl -i spec_template_regs.cheby
-- --gen-hdl
=spec_template_regs.vhd
-i spec_template_regs.cheby
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
@@ -28,17 +28,24 @@ entity spec_template_regs is
metadata_data_o
:
out
std_logic_vector
(
31
downto
0
);
-- offset to the application metadata
app_offset_i
:
in
std_logic_vector
(
31
downto
0
);
-- Thermometer and unique id
therm_id_i
:
in
t_wishbone_master_in
;
therm_id_o
:
out
t_wishbone_master_out
;
csr_app_offset_i
:
in
std_logic_vector
(
31
downto
0
);
csr_resets_global_o
:
out
std_logic
;
csr_resets_appl_o
:
out
std_logic
;
-- presence lines for the fmcs
csr_fmc_presence_i
:
in
std_logic_vector
(
31
downto
0
);
-- status of gennum
csr_gn4124_status_i
:
in
std_logic_vector
(
31
downto
0
);
-- Set when calibration is done.
csr_ddr_status_calib_done_i
:
in
std_logic
;
csr_pcb_rev_rev_i
:
in
std_logic_vector
(
3
downto
0
);
-- Thermometer and unique id
therm_id_i
:
in
t_wishbone_master_in
;
therm_id_o
:
out
t_wishbone_master_out
;
-- i2c controllers to the fmcs
fmc_i2c_i
:
in
t_wishbone_master_in
;
fmc_i2c_o
:
out
t_wishbone_master_out
;
...
...
@@ -72,14 +79,14 @@ architecture syn of spec_template_regs is
signal
wb_wip
:
std_logic
;
signal
metadata_rack
:
std_logic
;
signal
metadata_re
:
std_logic
;
signal
csr_resets_global_reg
:
std_logic
;
signal
csr_resets_appl_reg
:
std_logic
;
signal
therm_id_re
:
std_logic
;
signal
therm_id_wt
:
std_logic
;
signal
therm_id_rt
:
std_logic
;
signal
therm_id_tr
:
std_logic
;
signal
therm_id_wack
:
std_logic
;
signal
therm_id_rack
:
std_logic
;
signal
csr_resets_global_reg
:
std_logic
;
signal
csr_resets_appl_reg
:
std_logic
;
signal
fmc_i2c_re
:
std_logic
;
signal
fmc_i2c_wt
:
std_logic
;
signal
fmc_i2c_rt
:
std_logic
;
...
...
@@ -118,7 +125,7 @@ begin
wb_en
<=
wb_cyc_i
and
wb_stb_i
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
wb_rip
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
wb_rip
<=
(
wb_rip
or
(
wb_en
and
not
wb_we_i
))
and
not
rd_ack_int
;
...
...
@@ -127,7 +134,7 @@ begin
rd_int
<=
(
wb_en
and
not
wb_we_i
)
and
not
wb_rip
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
wb_wip
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
wb_wip
<=
(
wb_wip
or
(
wb_en
and
wb_we_i
))
and
not
wr_ack_int
;
...
...
@@ -143,7 +150,7 @@ begin
-- Assign outputs
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
metadata_rack
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
metadata_rack
<=
metadata_re
and
not
metadata_rack
;
...
...
@@ -151,11 +158,13 @@ begin
end
process
;
metadata_data_o
<=
wb_dat_i
;
metadata_addr_o
<=
wb_adr_i
(
5
downto
2
);
csr_resets_global_o
<=
csr_resets_global_reg
;
csr_resets_appl_o
<=
csr_resets_appl_reg
;
-- Assignments for submap therm_id
therm_id_tr
<=
therm_id_wt
or
therm_id_rt
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
therm_id_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
therm_id_rt
<=
(
therm_id_rt
or
therm_id_re
)
and
not
therm_id_rack
;
...
...
@@ -169,13 +178,11 @@ begin
therm_id_o
.
sel
<=
(
others
=>
'1'
);
therm_id_o
.
we
<=
therm_id_wt
;
therm_id_o
.
dat
<=
wb_dat_i
;
csr_resets_global_o
<=
csr_resets_global_reg
;
csr_resets_appl_o
<=
csr_resets_appl_reg
;
-- Assignments for submap fmc_i2c
fmc_i2c_tr
<=
fmc_i2c_wt
or
fmc_i2c_rt
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
fmc_i2c_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
fmc_i2c_rt
<=
(
fmc_i2c_rt
or
fmc_i2c_re
)
and
not
fmc_i2c_rack
;
...
...
@@ -193,7 +200,7 @@ begin
-- Assignments for submap flash_spi
flash_spi_tr
<=
flash_spi_wt
or
flash_spi_rt
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
flash_spi_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
flash_spi_rt
<=
(
flash_spi_rt
or
flash_spi_re
)
and
not
flash_spi_rack
;
...
...
@@ -211,7 +218,7 @@ begin
-- Assignments for submap dma
dma_tr
<=
dma_wt
or
dma_rt
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
dma_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
dma_rt
<=
(
dma_rt
or
dma_re
)
and
not
dma_rack
;
...
...
@@ -229,7 +236,7 @@ begin
-- Assignments for submap vic
vic_tr
<=
vic_wt
or
vic_rt
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
vic_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
vic_rt
<=
(
vic_rt
or
vic_re
)
and
not
vic_rack
;
...
...
@@ -247,7 +254,7 @@ begin
-- Assignments for submap wrc_regs
wrc_regs_tr
<=
wrc_regs_wt
or
wrc_regs_rt
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
wrc_regs_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
wrc_regs_rt
<=
(
wrc_regs_rt
or
wrc_regs_re
)
and
not
wrc_regs_rack
;
...
...
@@ -264,11 +271,11 @@ begin
-- Process for write requests.
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
wr_ack_int
<=
'0'
;
therm_id_wt
<=
'0'
;
csr_resets_global_reg
<=
'0'
;
csr_resets_appl_reg
<=
'0'
;
therm_id_wt
<=
'0'
;
fmc_i2c_wt
<=
'0'
;
flash_spi_wt
<=
'0'
;
dma_wt
<=
'0'
;
...
...
@@ -294,28 +301,34 @@ begin
when
"00"
=>
case
wb_adr_i
(
3
downto
2
)
is
when
"00"
=>
-- Register app_offset
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
when
"01"
=>
-- Submap therm_id
therm_id_wt
<=
(
therm_id_wt
or
wr_int
)
and
not
therm_id_wack
;
wr_ack_int
<=
therm_id_wack
;
when
"10"
=>
case
wb_adr_i
(
3
downto
2
)
is
when
"00"
=>
-- Register csr_app_offset
when
"01"
=>
-- Register csr_resets
if
wr_int
=
'1'
then
csr_resets_global_reg
<=
wb_dat_i
(
0
);
csr_resets_appl_reg
<=
wb_dat_i
(
1
);
end
if
;
wr_ack_int
<=
wr_int
;
when
"
01
"
=>
when
"
10
"
=>
-- Register csr_fmc_presence
when
"11"
=>
-- Register csr_gn4124_status
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
when
"01"
=>
case
wb_adr_i
(
3
downto
2
)
is
when
"00"
=>
-- Register csr_ddr_status
when
"01"
=>
-- Register csr_pcb_rev
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
when
"11"
=>
-- Submap therm_id
therm_id_wt
<=
(
therm_id_wt
or
wr_int
)
and
not
therm_id_wack
;
wr_ack_int
<=
therm_id_wack
;
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
...
...
@@ -358,7 +371,7 @@ begin
-- Process for registers read.
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
rd_ack1_int
<=
'0'
;
reg_rdat_int
<=
(
others
=>
'X'
);
elsif
rising_edge
(
clk_i
)
then
...
...
@@ -374,27 +387,39 @@ begin
when
"00"
=>
case
wb_adr_i
(
3
downto
2
)
is
when
"00"
=>
-- app_offset
reg_rdat_int
<=
app_offset_i
;
-- csr_app_offset
reg_rdat_int
<=
csr_app_offset_i
;
rd_ack1_int
<=
rd_int
;
when
"01"
=>
-- csr_resets
reg_rdat_int
(
0
)
<=
csr_resets_global_reg
;
reg_rdat_int
(
1
)
<=
csr_resets_appl_reg
;
rd_ack1_int
<=
rd_int
;
when
"10"
=>
-- csr_fmc_presence
reg_rdat_int
<=
csr_fmc_presence_i
;
rd_ack1_int
<=
rd_int
;
when
"11"
=>
-- csr_gn4124_status
reg_rdat_int
<=
csr_gn4124_status_i
;
rd_ack1_int
<=
rd_int
;
when
others
=>
rd_ack1_int
<=
rd_int
;
end
case
;
when
"01"
=>
when
"10"
=>
case
wb_adr_i
(
3
downto
2
)
is
when
"00"
=>
-- csr_resets
reg_rdat_int
(
0
)
<=
csr_resets_global_reg
;
reg_rdat_int
(
1
)
<=
csr_resets_appl_reg
;
-- csr_ddr_status
reg_rdat_int
(
0
)
<=
csr_ddr_status_calib_done_i
;
rd_ack1_int
<=
rd_int
;
when
"01"
=>
-- csr_
fmc_presence
reg_rdat_int
<=
csr_fmc_presence
_i
;
-- csr_
pcb_rev
reg_rdat_int
(
3
downto
0
)
<=
csr_pcb_rev_rev
_i
;
rd_ack1_int
<=
rd_int
;
when
others
=>
rd_ack1_int
<=
rd_int
;
end
case
;
when
"11"
=>
when
others
=>
rd_ack1_int
<=
rd_int
;
end
case
;
...
...
@@ -446,30 +471,42 @@ begin
when
"00"
=>
case
wb_adr_i
(
3
downto
2
)
is
when
"00"
=>
-- app_offset
-- csr_app_offset
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01"
=>
-- csr_resets
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"10"
=>
-- csr_fmc_presence
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"11"
=>
-- csr_gn4124_status
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
others
=>
rd_ack_int
<=
rd_int
;
end
case
;
when
"01"
=>
-- Submap therm_id
therm_id_re
<=
rd_int
;
wb_dat_o
<=
therm_id_i
.
dat
;
rd_ack_int
<=
therm_id_rack
;
when
"10"
=>
case
wb_adr_i
(
3
downto
2
)
is
when
"00"
=>
-- csr_
reset
s
-- csr_
ddr_statu
s
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"01"
=>
-- csr_
fmc_presence
-- csr_
pcb_rev
wb_dat_o
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
others
=>
rd_ack_int
<=
rd_int
;
end
case
;
when
"11"
=>
-- Submap therm_id
therm_id_re
<=
rd_int
;
wb_dat_o
<=
therm_id_i
.
dat
;
rd_ack_int
<=
therm_id_rack
;
when
others
=>
rd_ack_int
<=
rd_int
;
end
case
;
...
...
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