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Simple PCIe FMC carrier SPEC
Commit 1e8eacfe authored by Tristan Gingold's avatar Tristan Gingold
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spec_base: add g_DDR_DATA_SIZE.

parent a347c6df
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Showing with 29 additions and 43 deletions
hdl/rtl/spec_base_wr.vhd
View file @ 1e8eacfe
...@@ -48,6 +48,8 @@ entity spec_base_wr is ...@@ -48,6 +48,8 @@ entity spec_base_wr is
g_WITH_SPI : boolean := True; g_WITH_SPI : boolean := True;
g_WITH_WR : boolean := True; g_WITH_WR : boolean := True;
g_WITH_DDR : boolean := True; g_WITH_DDR : boolean := True;
-- Size of the DDR data port in bits (32 or 64)
g_DDR_DATA_SIZE : natural := 64;
-- Address of the application meta-data. 0 if none. -- Address of the application meta-data. 0 if none.
g_APP_OFFSET : std_logic_vector(31 downto 0) := x"0000_0000"; g_APP_OFFSET : std_logic_vector(31 downto 0) := x"0000_0000";
-- Number of user interrupts -- Number of user interrupts
...@@ -225,10 +227,17 @@ entity spec_base_wr is ...@@ -225,10 +227,17 @@ entity spec_base_wr is
-- Direct access to the DDR-3 -- Direct access to the DDR-3
-- Classic wishbone -- Classic wishbone
ddr_dma_clk_i : in std_logic; ddr_dma_clk_i : in std_logic := '0';
ddr_dma_rst_n_i : in std_logic; ddr_dma_rst_n_i : in std_logic := '0';
ddr_dma_wb_i : in t_wishbone_slave_data64_in; ddr_dma_wb_cyc_i : in std_logic := '0';
ddr_dma_wb_o : out t_wishbone_slave_data64_out; ddr_dma_wb_stb_i : in std_logic := '0';
ddr_dma_wb_adr_i : in std_logic_vector(31 downto 0) := (others => '0');
ddr_dma_wb_sel_i : in std_logic_vector((g_DDR_DATA_SIZE / 8) - 1 downto 0) := (others => '0');
ddr_dma_wb_we_i : in std_logic := '0';
ddr_dma_wb_dat_i : in std_logic_vector(g_DDR_DATA_SIZE - 1 downto 0) := (others => '0');
ddr_dma_wb_ack_o : out std_logic;
ddr_dma_wb_stall_o : out std_logic;
ddr_dma_wb_dat_o : out std_logic_vector(g_DDR_DATA_SIZE - 1 downto 0);
-- DDR FIFO empty flag -- DDR FIFO empty flag
ddr_wr_fifo_empty_o : out std_logic; ddr_wr_fifo_empty_o : out std_logic;
...@@ -1009,8 +1018,8 @@ begin -- architecture top ...@@ -1009,8 +1018,8 @@ begin -- architecture top
g_MEMCLK_PERIOD => 3000, g_MEMCLK_PERIOD => 3000,
g_SIMULATION => boolean'image(g_SIMULATION), g_SIMULATION => boolean'image(g_SIMULATION),
g_CALIB_SOFT_IP => "TRUE", g_CALIB_SOFT_IP => "TRUE",
g_P0_MASK_SIZE => 8, g_P0_MASK_SIZE => g_DDR_DATA_SIZE / 8,
g_P0_DATA_PORT_SIZE => 64, g_P0_DATA_PORT_SIZE => g_DDR_DATA_SIZE,
g_P0_BYTE_ADDR_WIDTH => 30, g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4, g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32, g_P1_DATA_PORT_SIZE => 32,
...@@ -1042,15 +1051,15 @@ begin -- architecture top ...@@ -1042,15 +1051,15 @@ begin -- architecture top
wb0_rst_n_i => ddr_dma_rst_n_i, wb0_rst_n_i => ddr_dma_rst_n_i,
wb0_clk_i => ddr_dma_clk_i, wb0_clk_i => ddr_dma_clk_i,
wb0_sel_i => ddr_dma_wb_i.sel, wb0_sel_i => ddr_dma_wb_sel_i,
wb0_cyc_i => ddr_dma_wb_i.cyc, wb0_cyc_i => ddr_dma_wb_cyc_i,
wb0_stb_i => ddr_dma_wb_i.stb, wb0_stb_i => ddr_dma_wb_stb_i,
wb0_we_i => ddr_dma_wb_i.we, wb0_we_i => ddr_dma_wb_we_i,
wb0_addr_i => ddr_dma_wb_i.adr, wb0_addr_i => ddr_dma_wb_adr_i,
wb0_data_i => ddr_dma_wb_i.dat, wb0_data_i => ddr_dma_wb_dat_i,
wb0_data_o => ddr_dma_wb_o.dat, wb0_data_o => ddr_dma_wb_dat_o,
wb0_ack_o => ddr_dma_wb_o.ack, wb0_ack_o => ddr_dma_wb_ack_o,
wb0_stall_o => ddr_dma_wb_o.stall, wb0_stall_o => ddr_dma_wb_stall_o,
p0_cmd_empty_o => open, p0_cmd_empty_o => open,
p0_cmd_full_o => open, p0_cmd_full_o => open,
...@@ -1119,12 +1128,9 @@ begin -- architecture top ...@@ -1119,12 +1128,9 @@ begin -- architecture top
ddr_reset_n_o <= '0'; ddr_reset_n_o <= '0';
ddr_we_n_o <= '0'; ddr_we_n_o <= '0';
ddr_rzq_b <= 'Z'; ddr_rzq_b <= 'Z';
ddr_dma_wb_o.dat <= (others => '0'); ddr_dma_wb_dat_o <= (others => '0');
ddr_dma_wb_o.ack <= '1'; ddr_dma_wb_ack_o <= '1';
ddr_dma_wb_o.stall <= '0'; ddr_dma_wb_stall_o <= '0';
ddr_wr_fifo_empty_o <= '0'; ddr_wr_fifo_empty_o <= '0';
end generate gen_without_ddr; end generate gen_without_ddr;
ddr_dma_wb_o.err <= '0';
ddr_dma_wb_o.rty <= '0';
end architecture top; end architecture top;
hdl/syn/golden_wr-150T/Manifest.py
View file @ 1e8eacfe
...@@ -13,6 +13,7 @@ syn_project = "spec_golden_wr.xise" ...@@ -13,6 +13,7 @@ syn_project = "spec_golden_wr.xise"
syn_tool = "ise" syn_tool = "ise"
syn_top = "spec_golden_wr" syn_top = "spec_golden_wr"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec" board = "spec"
ctrls = ["bank3_64b_32b" ] ctrls = ["bank3_64b_32b" ]
...@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ] ...@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ]
modules = { modules = {
"local" : [ "local" : [
"../../top/golden_wr", "../../top/golden_wr", "../../syn/common"
], ],
"git" : [ "git" : [
"https://ohwr.org/project/wr-cores.git", "https://ohwr.org/project/wr-cores.git",
......
hdl/top/full/spec_full.vhd
View file @ 1e8eacfe
...@@ -268,13 +268,6 @@ begin ...@@ -268,13 +268,6 @@ begin
ddr_dma_clk_i => clk_sys_62m5, ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n, ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_i.cyc => '0',
ddr_dma_wb_i.stb => '0',
ddr_dma_wb_i.adr => x"0000_0000",
ddr_dma_wb_i.sel => x"00",
ddr_dma_wb_i.we => '0',
ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
ddr_dma_wb_o => open,
clk_62m5_sys_o => clk_sys_62m5, clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n, rst_62m5_sys_n_o => rst_sys_62m5_n,
......
hdl/top/golden/spec_golden.vhd
View file @ 1e8eacfe
...@@ -143,13 +143,6 @@ begin ...@@ -143,13 +143,6 @@ begin
ddr_dma_clk_i => clk_sys_62m5, ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n, ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_i.cyc => '0',
ddr_dma_wb_i.stb => '0',
ddr_dma_wb_i.adr => x"0000_0000",
ddr_dma_wb_i.sel => x"00",
ddr_dma_wb_i.we => '0',
ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
ddr_dma_wb_o => open,
clk_62m5_sys_o => clk_sys_62m5, clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n, rst_62m5_sys_n_o => rst_sys_62m5_n,
......
hdl/top/golden_wr/spec_golden_wr.vhd
View file @ 1e8eacfe
...@@ -230,13 +230,6 @@ begin ...@@ -230,13 +230,6 @@ begin
ddr_dma_clk_i => clk_sys_62m5, ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n, ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_i.cyc => '0',
ddr_dma_wb_i.stb => '0',
ddr_dma_wb_i.adr => x"0000_0000",
ddr_dma_wb_i.sel => x"00",
ddr_dma_wb_i.we => '0',
ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
ddr_dma_wb_o => open,
clk_62m5_sys_o => clk_sys_62m5, clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n, rst_62m5_sys_n_o => rst_sys_62m5_n,
......
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