2.0.0 - 2020-07-30 ================== Added ----- - hdl: new testbench to test the DMA feature (read/write to DDR memory) in the new golden. - sw: basic Python module to handle DMA and FPGA programming - sw: user-space DMA interface in debugfs (read/write) - tst: add integration tests for DMA transfers Changed ------- - hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers. - hdl: Cleanup of top-levels, addition of DMA to the golden. Fixed ----- - hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by inadequate flow control. - hdl: typo in synthesis constraints.