[hdl] rework synthesis constraints (7ebae5ae) · Commits · Projects / Simple PCIe FMC carrier SPEC · GitLab

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7ebae5ae

Commit 7ebae5ae authored 5 years ago by Dimitris Lampridis

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[hdl] rework synthesis constraints

parent cb051180

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Changes 4

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Manifest.py 3 additions, 0 deletions

Manifest.py
hdl/syn/common/spec_template_common.ucf 155 additions, 148 deletions

hdl/syn/common/spec_template_common.ucf
hdl/syn/common/spec_template_ddr3.ucf 24 additions, 6 deletions

hdl/syn/common/spec_template_ddr3.ucf
hdl/syn/common/spec_template_wr.ucf 66 additions, 46 deletions

hdl/syn/common/spec_template_wr.ucf

with 248 additions and 200 deletions

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