SoC Course with Reference Designs
Project description
Introductory SoC course with reference designs based on the Xilinx Vitis Unified Software Development Platform and targeted to the Xilinx Zynq UltraScale+ MPSoC.
Specifications
This course applies the learn by example approach, introducing in each section the required theoretical concepts and then achieving a deeper understanding on the presented topics by performing practical exercises using the most important design tools and techniques.
Upon completion of the course, several software and hardware reference designs are created by following step-by-step detailed procedures including screenshots, commands and code snippets.
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Required Software
- Development machine with a supported Linux Operating System
- Xilinx Vitis Unified Software Development Platform
- Xilinx Vivado Design Suite (no additional license required)
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Required Hardware
- FARNELL ref 3050481: Ultra96-V2 Zynq UltraScale+ ZU3EG Single Board Computer
- FARNELL ref 3216978: Ultra96 Power Supply Kit, 12V, 4A 03AH7039
- FARNELL ref 2915522: Adapter Board, USB To JTAG/UART Adapter Module, For Ultra96 Development Board
- FARNELL ref 1617586: USB cable type A to micro type B, 1.5m, USB 2.0
Project Information
This is the syllabus for the SoC course, covering the main design concepts required to customize and bring-up embedded software in Zynq UltraScale+ MPSoC based hardware platforms. For each of the chapters in the proposed course sessions, the theoretical concepts are supported by practical exercises with detailed step-by-step procedures so that self-learning can be easily accomplished.
Session 0
Installing the required tools, setting the Ultra96-V2 hardware and testing the set-up before the course.
Session 1
Introducing the MPSoC architecture, understanding the booting sequence, configuring the MPSoC Processing System in Vivado, understanding the exported hardware information to be used by the Vitis software tools, and practicing with standalone software development.
- MPSoC Architecture Overview
- Vivado Design with Standalone Processing System
- MPSoC Boot Process
- Reverse Engineering the XSA File
- Embedded Software Hierarchy in Vitis
- Vitis Hello World Demo
Session 2
Managing peripherals in the Processing System, communicating different cores in the MPSoC, understanding the address space hierarchy in the MPSoC, creating custom AXI peripherals with Vivado, and using peripherals placed in the Programmable Logic.
- Standalone Peripheral Drivers
- Inter Processor Interrupts and Message Buffers
- MPSoC Address Map
- Vivado Design with Custom Programmable Logic
- Standalone Peripheral Drivers (PL)
Session 3
Understanding, configuring and building all of the software components required to successfully boot a Linux runtime in a custom MPSoC based hardware design, and using the Userspace I/O drivers to handle custom peripherals implemented in the Programmable Logic.
- Xilinx Software Command Line Tool (XSCT)
- Hardware Software Interface (HSI)
- ARM Trusted Firmware (ATF)
- Universal Boot Loader (U-Boot)
- Linux Kernel Image and Modules
- Linux Runtime and User Space Drivers
Bibliography
Contacts
Status
Date | Event |
---|---|
05-05-2020 | CERN ordered SoC reference design with documentation. |
10-06-2020 | Course kick-start session with CERN alumni from BE-CO-HT. |
18-06-2020 | Course final session successfully performed. |
22-06-2020 | Course content reviewed and released for public access. |
22 Jun 2020