Zynq UltraScale+ MPSoC Architecture Overview

• Block Diagram
• Processing Units
• Power Management
  • Power Domains
  • Power Modes
• I/O Peripherals
• AMBA AXI4
  • Interconnect
  • Master Interfaces
  • Slave Interfaces

Block Diagram

Processing Units

In the MPSoC, there are two main blocks with different specialized processing units:

• Processing System (PS):
  • APU: Quad or Dual core Cortex-A53 application processing unit. ARM v8 64-bit architecture. It supports:
    • Asymmetric Multi Processing (AMP): each core running different applications (limited support due to shared HW infrastructure).
    • Symmetric Multi Processing (SMP): all of the cores running the same software (e.g. Linux operating system).
  • RPU: Dual core Cortex-R5 real-time processing unit. ARM v7 32-bit architecture.
    • Split Mode: each core running different applications as totally independent CPUs.
    • Lockstep Mode: both cores running the same application for higher security.
  • PMU: Platform management unit based on triple module redundant Microblaze processor.
  • CSU: Configuration Security Unit based on triple module redundant Microblaze processor.
  • GPU: MALI-400 graphic processing unit (available in EG and EV MPSoC families).
• Programmable Logic (PL):
  • VCU: Video control unit with hardware codecs and compression (available in EV MPSoC family).
  • RF: Radio frequency unit with up to 16 channels RF-ADCs and RF-DACs (available in RFSoC family).

Power Management

The power management in the MPSoC is handled by the Platform Management Unit (PMU).

Power Domains

There are four different power domains in the MPSoC devices:

• Low Power Domain (LPD): RPU, PMU, CSU, LPD_DMA, and LPD peripherals
• Full Power Domain (FPD): APU, FPD_DMA, and FPD peripherals
• PL Power Domain (PLPD): Programmable logic
• Battery Power Domain (BPD): Real Time clock and Battery-backed RAM (BBRAM) for secure configuration key.

Each power domain can be individually isolated. The platform management unit (PMU) on the LPD facilitates the isolation of each of the power domains. Additionally, the isolation can be turned on automatically when one of the power supplies of the corresponding power domain is accidentally powered down. Since each power domain can be individually isolated, functional isolation (an important aspect of safety and security applications) is possible.

As an application example that we will see later, because the PS and PL resides in two different power domains, the Processing System can be used as a full-featured SoC without powering up the Programmable Logic.

Power Modes

The MPSoC supports three different operational power modes:

• Battery Powered Mode: maintain critical information over the time when MPSoC is powered-off.
• Low Power Mode: only the devices in the LPD are powered up.
• Full Power Mode: all the power domains are activated, including Programmable Logic.

I/O Peripherals

The Zynq UltraScale+ MPSoC features a vast amount of I/O peripherals placed in the different power domains:

• Low Power Domain (LPD):
  • General Purpose I/O (GPIO)
  • Quad SPI Flash Memory (QSPI)
  • NAND ONFI 3.1 Controller.
  • 4x Gigabit Ethernet MAC
  • 2x USB3
  • 2x Secure Digital IO (SDIO) for SD / eMMC.
  • 2x Serial Peripheral Interface (SPI).
  • 2x CAN
  • 2x I2C
  • 2x UART
  • System Monitor
• Full Power Domain (FPD):
  • PCIe Gen2 x1/x2/x4
  • 2x Serial Advanced Technology Attachment (SATA)
  • 2x Display Port 1.2 (DP)
• Programmable Logic Power Domain (PLPD):
  • PCIe Gen3 x16, Gen4 x8.
  • 100G Ethernet.
  • 150G Interlaken v1.2.
  • GTH and GTY Transceivers.

The peripherals' I/O interfaces can be router to the Multiplexed I/O (MIO) and the Extended Multiplexed I/O (EMIO).

• There are up to 78 MIO ports divided in three banks available from the processing system and the MIO itself resides in the Low Power Domain.
• As the number of MIO ports is limited, many of the available peripherals can be routed to the programmable logic through the Extended MIO (EMIO).

AMBA AXI4

The Zynq UltraScale+ MPSoC provides AMBA AXI4 capabilities for high performance data communications.

Interconnect

There are three main AMBA interconnect blocks:

• Full Power Domain (FPD):
  • AXI Cache-Coherent Interconnect (CCI)
  • Central/Core Switch
• Low-Power Domain (LPD):
  • LPD Switch

The system provides the following AMBA AXI4 compliant interfaces for PS-PL communications:

Master Interfaces

The PS acts as master and the PL as slave.

• 3x HPM: PS General Purpose Master interfaces (32, 64, and 128 bits width, default 128)
  • 2x HPM FPD: From full power domain
  • 1x HPM LPD: From low power domain (low latency from peripherals and RPU)

Slave Interfaces

The PS acts as slave and the PL as master-

• 7x PL General Purpose Master interfaces (32, 64, and 128 bits width, default 128):
  • 2x S-AXI HPC FPD: access to full power domain
  • 4x S-AXI HP FPD: access to full power domain and DDR controller
  • 1x AXI LPD: access to low power domain
• 1x S-AXI ACE: PL Master AXI Coherency Extension (ACE) interface for coherent I/O to A53 L1 and L2 cache (128 bits width)
• 1x S-AXI ACP-FPD: PL Master ACP interface for L2 cache allocation from PL masters, limited to 64-byte cache line transfers (128 bits width).