PXIe controller COM Express based
Project description
This project is a PXIe system controller that is based on a COM Express Computer on Module.
Main Features
- Compliance with COM Express basic Pin-out type 6
- Compliance with PXIe standard for 3U system controller slot
- PCIe lane designed to meet PCIe GEN 3 specification
- 16x PCIe lanes routed to the PXIe backplane connector
- PXIe trigger controller (FPGA)
- Possibility to install a full size mSATA SSD (supports mini mSATA)
- Front panel
- 1x RS232 port DSUB9 connector
- 4x USB 2.0
- 2x USB 3.0
- 1x 10/100/1000 Ethernet LAN
- 1x DisplayPort
- 1x SMB PXIe trigger line
- Xilinx XC7A50T-1FTG256C FPGA for trigger management
Project information
- Official production documentation
- PXIe controller COM Express based carrier Design Study
- Schematics
- Users
- Software
- Frequently Asked Questions
Contacts
Commercial producers
- Foreseen to be commercially available once the development is finished.
General questions about project
- Paul Peronnard - CERN
- Erik van der Bij - CERN
Status
Date | Event |
---|---|
24-01-2019 | First specifications written. |
05-04-2019 | Order sent out for a pre-study. |
21-06-2019 | Pre-study ready. |
27-06-2019 | Review of pre-study. |
24-10-2019 | Start of schematics design. |
05-12-2019 | First version of schematics design (v0.1) made. Review will be held. |
09-04-2020 | Schematics review held. |
06-2020 | PCB layout in progress. |
08-2020 | PCB ready for review. |
10-2020 | PCB ready for manufacturing. |
15-12-2020 | Five V0.4 prototypes ordered, for delivery by |
26-05-2021 | Five V0.4 modules ready and tested. |
04-06-2021 | V1.0 design will be made by CERN's design office. |
30-06-2021 | Order made for a Production Test System (PTS). |
30 June 2021