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PXIe controller COM Express based
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Last edited by Erik van der Bij Feb 14, 2023
Page history

PXIe controller COM Express based

Project description

This project is a PXIe system controller that is based on a COM Express Computer on Module.

2 1

Main Features

  • Compliance with COM Express module:
    • Basic 'b'-type
    • Pin-out type 6
    • The used COM Express Basic module needs to be configurable to 4x PCIe x4 lanes
    • Heat spreader allows for 42 Watt dissipation in airflow of 1.0 - 1.5 m/s
  • Compliance with PXIe standard for 3U system controller slot
  • PCIe lane designed to meet PCIe GEN 3 specification
  • 16x PCIe lanes routed to the PXIe backplane connector
  • PXI trigger controller (FPGA)
  • Possibility to install a full size mSATA SSD (supports mini mSATA)
  • Front panel
    • 1x RS232 port DSUB9 connector
    • 4x USB 2.0
    • 2x USB 3.0
    • 1x 10/100/1000 Ethernet LAN
    • 1x DisplayPort
    • 1x SMB Trigger line
  • Xilinx XC7A50T-1FTG256C FPGA for trigger management

Project information

  • Official production documentation
    • EDA-04509 - PXIe Controller COM Express based
    • EDA-04510 - PXIe Controller COM Express based - Front Panel Card
    • Assembly Instructions - PXIeCOMe-19752
  • PXIe controller COM Express based testing support - project
  • PXIe Communication Tester - PXCT - project with testing hardware.
  • PXIe controller COM Express based carrier Design Study
    • Block diagram
  • Schematics
  • Users
  • Software
  • Frequently Asked Questions
  • User manual

Contacts

Commercial producers

  • Foreseen to be commercially available once the development is finished.

General questions about project

  • Erik van der Bij - CERN
  • Paul Peronnard - CERN

Status

Date Event
24-01-2019 First specifications written.
05-04-2019 Order sent out for a pre-study.
21-06-2019 Pre-study ready.
27-06-2019 Review of pre-study.
24-10-2019 Start of schematics design.
05-12-2019 First version of schematics design (v0.1) made. Review will be held.
09-04-2020 Schematics review held.
06-2020 PCB layout in progress.
08-2020 PCB ready for review.
10-2020 PCB ready for manufacturing.
15-12-2020 Five V0.4 prototypes ordered, for delivery by end-March end-May 2021.
26-05-2021 Five V0.4 modules ready and tested.
04-06-2021 V1.0 design will be made by CERN's design office.
30-06-2021 Order made for a Production Test System (PTS).
31-08-2021 Change of responsible (was PP).
04-10-2021 Production Test System (PTS) ready. Needs changes between V0.4 and V1.0.
22-11-2021 Project passed to CERN's design office for production preparation
02-03-2022 V1.0 design released
09-03-2022 V1.0 design needs update as based on v0.3 and not v0.4.
25-05-2022 V1.0 design corrected. To be verified to be production ready.
22-11-2022 V1.0 design ready for the production of a small preseries.
19-12-2022 Engineering run of 20 PXIe-COMe boards to be delivered in May 2023.

14 February 2023

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