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PXIe controller COM Express based
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PXIe controller COM Express based
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EDA-04509 Stickers
#78
· opened
Jul 04, 2023
by
René Bakker
V1-1
CLOSED
6
updated
Oct 02, 2023
EDA-04509-V1-0_fp Wrong dimension
#77
· opened
Jul 04, 2023
by
René Bakker
V1-1
CLOSED
1
updated
Sep 25, 2023
V1 - Front panel files do not contain OHL text
#61
· opened
Jun 30, 2022
by
Erik van der Bij
CLOSED
1
updated
Sep 22, 2022
V1 - Schematics use OHL-S. Should be "CERN-OHL-W-2.0+"
#60
· opened
Jun 30, 2022
by
Erik van der Bij
CLOSED
1
updated
Sep 22, 2022
Assembly instructions file: licence under CC-BY-SA and add on ohwr/edms
#59
· opened
Nov 09, 2021
by
Erik van der Bij
CLOSED
11
updated
Jul 10, 2023
Use of LINKCAP
#57
· opened
Sep 22, 2021
by
René Bakker
To Do
CLOSED
1
updated
Mar 03, 2022
Use of SYSEN_N
#56
· opened
Sep 22, 2021
by
René Bakker
To Do
CLOSED
1
updated
Mar 03, 2022
Forced power on
#54
· opened
Sep 22, 2021
by
René Bakker
To Do
CLOSED
2
updated
Aug 23, 2023
IC22 traces wider than component pads
#48
· opened
Sep 28, 2020
by
Tomasz Wlostowski
CLOSED
1
updated
Oct 06, 2020
[L8] P3V3AUX pad barely touching the via
#47
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
Possible acid traps in polygons
#46
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
Add more stitching vias to connect GND planes together
#45
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
3
updated
Oct 08, 2020
Diff pairs should be deskewed close to source or receiver which is not always the case
#44
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
[L1] X:97mm Y:91mm move SER1_RX track further away from M1 mounting hole
#43
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
[L1] X:80mm Y:84mm fix SMB_CLK track routing
#42
· opened
Sep 23, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
[L1] IC21 layout could be optimised
#41
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
7
updated
Oct 09, 2020
PXI_TRIG7 is connected to multiple FPGA pins, was this intentional?
#40
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 07, 2020
[L1] X:88mm Y:12mm use wider thermal reliefs to pass required current on P1V rail
#39
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
[L1] X:127mm Y:12mm use wider thermal reliefs to pass required current on P1V8 rail
#38
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
Add copper balancing pattern in front and bottom layers
#37
· opened
Sep 22, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Oct 06, 2020
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