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P
PXIe controller COM Express based testing support
Commit ec1d281d authored by Joseph Tagg's avatar Joseph Tagg
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Updated to newest version from December 2022. This should be called version 1.1

parent 6d536ce5
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pts/test/pxiecome/python/COMe_GPIO.py
View file @ ec1d281d
......@@ -6,6 +6,14 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-12-15 INCAA Computers
# Added label to _parameters
# Added _get_baseaddress() to find the base address
# Added _get_gpiochip_label()
# Added baseaddr()
#------------------------------------------------------------------------
import sys
import os
......@@ -21,15 +29,18 @@ Simple interface to COMe GPIO interface
class COMe_GPIO(Item):
_parameters = {'addr':['Base address', 'Base GPIO sysfs address', 504, int],
'gpi_offset':['GPI address offset', 'Offset GPI sysfs address', 0, int],
'gpo_offset':['GPO address offset', 'Offset GPO sysfs address', 4, int]}
_parameters = {'addr':['Base address', 'Base GPIO sysfs address', 0, int],
'label':['gpiochip device label', 'Label of the sysfs gpiochip', "gpio-kempld", str],
'gpi_offset':['GPI address offset', 'Offset GPI sysfs address', 0, int],
'gpo_offset':['GPO address offset', 'Offset GPO sysfs address', 4, int]}
IN, OUT = 'in', 'out'
def __init__(self, *args, **kwargs):
"""The initializer doesn't connect to the device."""
Item.__init__(self, *args, **kwargs)
if (self.addr == 0):
self.addr = self._get_baseaddress()
self.gpo_base = self.addr + self.gpo_offset
self.gpi_base = self.addr + self.gpi_offset
......@@ -43,6 +54,29 @@ class COMe_GPIO(Item):
status = e.returncode
return output, status
def _get_baseaddress(self):
cmd_cd = "cd /sys/class/gpio"
cmd_ls = "ls -d gpiochip*"
sysfs_shell_cmd = cmd_cd + "; " + cmd_ls
output, status = self._shell(sysfs_shell_cmd)
base = 0
if status == 0:
output_lines = output.split('\n')
for line in output_lines:
line = line.lstrip()
line = line.rstrip()
sbase = line.replace("gpiochip", "")
ibase = int(sbase)
label = self._get_gpiochip_label(ibase)
if base == 0 and label == self.label:
base = ibase
return base
def _get_gpiochip_label(self, base):
sysfs_cmd = "cat /sys/class/gpio/gpiochip%d/label" % (base)
output, status = self._shell(sysfs_cmd)
return (output)
def _unexport(self, chippin):
sysfs_cmd_unexport = "echo %d > /sys/class/gpio/unexport" % (chippin)
output, status = self._shell(sysfs_cmd_unexport)
......@@ -121,6 +155,9 @@ class COMe_GPIO(Item):
def gpi(self, pin):
gpio_pin = int(pin) + self.gpi_offset
return int(self._get_value(gpio_pin))
def baseaddr(self):
return self.addr
if __name__ == "__main__":
main()
......
pts/test/pxiecome/python/COMe_info.py 0 → 100644
View file @ ec1d281d
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
import sys
import time
import os
import subprocess
# Add common modules and libraries location to path
sys.path.append('../../../')
from ptsexcept import *
from ptspxiecome import *
"""
COMe module used
"""
def main (default_directory='.'):
print "COMe Module used within the setup:"
print " bios_date: " + COMe_module_attrib('bios_date')
print " bios_vendor: " + COMe_module_attrib('bios_vendor')
print " bios_version: " + COMe_module_attrib('bios_version')
print " board_asset_tag: " + COMe_module_attrib('board_asset_tag')
print " board_name: " + COMe_module_attrib('board_name')
print " board_serial: " + COMe_module_attrib('board_serial')
print " board_vendor: " + COMe_module_attrib('board_vendor')
print " board_version: " + COMe_module_attrib('board_version')
print " chassis_asset_tag: " + COMe_module_attrib('chassis_asset_tag')
print " chassis_serial: " + COMe_module_attrib('chassis_serial')
print " chassis_type: " + COMe_module_attrib('chassis_type')
print " chassis_vendor: " + COMe_module_attrib('chassis_vendor')
print " chassis_version: " + COMe_module_attrib('chassis_version')
print " product_family: " + COMe_module_attrib('product_family')
print " product_name: " + COMe_module_attrib('product_name')
print " product_serial: " + COMe_module_attrib('product_serial')
print " product_sku: " + COMe_module_attrib('product_sku')
print " product_uuid: " + COMe_module_attrib('product_uuid')
print " product_version: " + COMe_module_attrib('product_version')
print " sys_vendor: " + COMe_module_attrib('sys_vendor')
print " uevent: " + COMe_module_attrib('uevent')
print " modalias: " + COMe_module_attrib('modalias')
if __name__ == '__main__' :
main()
pts/test/pxiecome/python/PXIeCOMe_tFPGA.py
View file @ ec1d281d
......@@ -6,19 +6,27 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-11-14 INCAA Computers
# Added import of ptspxiecome
# Added COM1_DEVICE as device
#------------------------------------------------------------------------
from ptspxiecome import *
from COMe_Serial import *
"""
Interface to PXIeCOMe tFPGA via COMe serial interface
"""
COM1_DEVICE = COMe_module_com1_device()
class PXIeCOMe_tFPGA(COMe_Serial):
def __init__(self):
"""The initializer doesn't connect to the device."""
COMe_Serial.__init__(self, device='/dev/ttyS1', bauds=115200)
COMe_Serial.__init__(self, device=COM1_DEVICE, bauds=115200)
# pxid: PXI_TRIG direction (pxi_trig7_t[2:0], pxi_trig_t[7:0]) (0:output, 1:input)
......
pts/test/pxiecome/python/flash_v2/vivado_lab.jou 0 → 100644
View file @ ec1d281d
#-----------------------------------------------------------
# Vivado Lab Edition v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
#
# Start of session at: Thu Dec 15 11:34:35 2022
# Process ID: 27203
# Current directory: /home/user/pts/test/pxiecome/python/flash_v2
# Command line: vivado_lab -mode batch -source vivado_flash.tcl -tclargs -url localhost:3121 -flash s25fl128sxxxxxx1-spi-x1_x2_x4 -mcs_file ../../gateware/PXIeCOMe_tFPGA.mcs -addr_range use_file -erase 1 -blank_check 0 -program 1 -verify 1
# Log file: /home/user/pts/test/pxiecome/python/flash_v2/vivado_lab.log
# Journal file: /home/user/pts/test/pxiecome/python/flash_v2/vivado_lab.jou
#-----------------------------------------------------------
source vivado_flash.tcl
pts/test/pxiecome/python/flash_v2/vivado_lab.log 0 → 100644
View file @ ec1d281d
#-----------------------------------------------------------
# Vivado Lab Edition v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
#
# Start of session at: Thu Dec 15 11:34:35 2022
# Process ID: 27203
# Current directory: /home/user/pts/test/pxiecome/python/flash_v2
# Command line: vivado_lab -mode batch -source vivado_flash.tcl -tclargs -url localhost:3121 -flash s25fl128sxxxxxx1-spi-x1_x2_x4 -mcs_file ../../gateware/PXIeCOMe_tFPGA.mcs -addr_range use_file -erase 1 -blank_check 0 -program 1 -verify 1
# Log file: /home/user/pts/test/pxiecome/python/flash_v2/vivado_lab.log
# Journal file: /home/user/pts/test/pxiecome/python/flash_v2/vivado_lab.jou
#-----------------------------------------------------------
source vivado_flash.tcl
# open_hw_manager
# array set optional [list -mcs_file "" -sec_mcs "" -url "localhost:3121" -flash "mx25u51245g-spi-x1_x2_x4_x8" -addr_range "use_file" -erase '1' -blank_check '0' -program '1' -verify '1' {*}$argv]
# set mcs_file $optional(-mcs_file)
# set sec_mcs $optional(-sec_mcs)
# set url $optional(-url)
# set flash $optional(-flash)
# set addr_range $optional(-addr_range)
# set erase $optional(-erase)
# set blank_check $optional(-blank_check)
# set program $optional(-program)
# set verify $optional(-verify)
# connect_hw_server -url ${url}
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3414] Connected to existing cs_server.
# set target_list [get_hw_targets]
# foreach i $target_list {
# open_hw_target [get_hw_targets ${i}]
# create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts $flash] 0];
# set_property PROGRAM.BLANK_CHECK $blank_check [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]];
# set_property PROGRAM.ERASE $erase [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]];
# set_property PROGRAM.CFG_PROGRAM $program [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]];
# set_property PROGRAM.VERIFY $verify [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]];
# set_property PROGRAM.ADDRESS_RANGE $addr_range [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]];
#
# if {[regexp -nocase {spi-x1_x2_x4_x8} $flash]} {
# set_property PROGRAM.FILES [list $mcs_file $sec_mcs] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]];
# } else {
# set_property PROGRAM.FILES $mcs_file [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]];
# }
#
# if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; };
#
# program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
# close_hw_target [current_hw_target]
# }
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000013e2330901
INFO: [Labtools 27-3164] End of startup status: HIGH
Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0
Performing Erase Operation...
Erase Operation successful.
Performing Program and Verify Operations...
Program/Verify Operation successful.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:00.08 ; elapsed = 00:01:14 . Memory (MB): peak = 2951.477 ; gain = 4.000 ; free physical = 9814 ; free virtual = 15384
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Xilinx/000013e2330901
# disconnect_hw_server [current_hw_server]
# close_hw_manager
****** Webtalk v2021.1 (64-bit)
**** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /home/user/pts/test/pxiecome/python/flash_v2/.Xil/vivado_lab-27203-pc-PXIeCOMe-test/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Thu Dec 15 11:35:56 2022...
INFO: [Common 17-206] Exiting vivado_lab at Thu Dec 15 11:35:56 2022...
pts/test/pxiecome/python/flash_v2/webtalk.jou 0 → 100644
View file @ ec1d281d
#-----------------------------------------------------------
# Webtalk v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
#
# Start of session at: Thu Dec 15 11:35:56 2022
# Process ID: 27361
# Current directory: /home/user/pts/test/pxiecome/python/flash_v2
# Command line: wbtcv -mode batch -source /home/user/pts/test/pxiecome/python/flash_v2/.Xil/vivado_lab-27203-pc-PXIeCOMe-test/webtalk/labtool_webtalk.tcl -notrace
# Log file: /home/user/pts/test/pxiecome/python/flash_v2/webtalk.log
# Journal file: /home/user/pts/test/pxiecome/python/flash_v2/webtalk.jou
#-----------------------------------------------------------
source /home/user/pts/test/pxiecome/python/flash_v2/.Xil/vivado_lab-27203-pc-PXIeCOMe-test/webtalk/labtool_webtalk.tcl -notrace
pts/test/pxiecome/python/flash_v2/webtalk.log 0 → 100644
View file @ ec1d281d
#-----------------------------------------------------------
# Webtalk v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
#
# Start of session at: Thu Dec 15 11:35:56 2022
# Process ID: 27361
# Current directory: /home/user/pts/test/pxiecome/python/flash_v2
# Command line: wbtcv -mode batch -source /home/user/pts/test/pxiecome/python/flash_v2/.Xil/vivado_lab-27203-pc-PXIeCOMe-test/webtalk/labtool_webtalk.tcl -notrace
# Log file: /home/user/pts/test/pxiecome/python/flash_v2/webtalk.log
# Journal file: /home/user/pts/test/pxiecome/python/flash_v2/webtalk.jou
#-----------------------------------------------------------
source /home/user/pts/test/pxiecome/python/flash_v2/.Xil/vivado_lab-27203-pc-PXIeCOMe-test/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Thu Dec 15 11:35:56 2022...
pts/test/pxiecome/python/ptspxiecome.py
View file @ ec1d281d
......@@ -6,6 +6,22 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-11-15 INCAA Computers
# Added documentation
# Changed COMe_module_settings to include the bios_version
# Added com0_device and com1_device within COMe_module_settings
# Added the COMe-bTL6 BIOS version BTL6R901 within COMe_module_settings
# Added COMe_bios_version()
# Added COMe_module_com0_device() and COMe_module_com1_device()
# 2022-12-15 INCAA Computers
# Changed documentation
# Removed gpio_base_addr (base addr of the gpio is now set dynamically)
# Removed COMe_module_gpio_base_addr
# Added gpiochip_label within COMe_module_settings
# Added COMe_module_gpiochip_label
#------------------------------------------------------------------------
import sys
import time
......@@ -14,20 +30,89 @@ import subprocess
"""
PXIeCOMe PTS common functions and settings
The setting which support the possibility to use serveral different COMe modules
are available using COMe_module_settings.
This COMe_module_settings consists of a heirarchy using the board_name and bios_vesion.
board_name
This is the value which is returned by the shell command 'cat /sys/class/dmi/id/board_name'
bios_vesion
This is the value which is returned by the shell command 'cat /sys/class/dmi/id/bios_version'
gpiochip_label
The device label of the gpio chip which provides access to the COMe module GPI[0:3] and
GPO[0:3] pins.
Use the shell command 'll /sys/class/gpio' or 'ls -l /sys/class/gpio' to see which gpio
chips are avaible.
For Kontron boards the one using the device kempld-gpio should be used. The number XXX
within gpiochipXXX is the gpio base address, which has to be found dynamically based on
the label of the gpio chip.
The shell command 'cat /sys/class/gpio/gpiochip1016/label' will return the value for
gpiochip_label. For Kontron boards this will be 'gpio-kempld'.
i2c_port
The port number for the i2c port which provides access to the COMe module I2C I2C_CK and
I2C_DAT pins.
Use the shell command 'i2cdetect -l' to show the list of ports.
For Kontron boards the i2c adapter 'i2c-kempld' should be used and the i2c-x shows with x
the port number. So when 'i2c-kempld' is connected to i2c-9, i2c_port should be 9.
smbus_port
The port number for the SMBus port which provides access to the COMe module SMBus SMB_CK
and SMB_DAT pins.
Use the shell command 'i2cdetect -l' to show the list of ports.
For Kontron boards the SMBus adapter 'SMBus CMI adapter cmi' should be used and the i2c-x
shows with x the port number. So when 'SMBus CMI adapter cmi' is connected to i2c-7,
smbus_port should be 7.
net_device
The network device which provides access to the COMe module GBE0 interface pins.
Use the shell command 'll /sys/class/net' should show which device is not virtual.
com0_device
The serial ports (usually named COM0 within the BIOS) which provide access to the COMe
module serial port SER0_RX and SER0_TX.
Use the shell command 'dmesg | grep ttyS' to show which uart com port uses which ttyS device.
For Kontron boards SER0/COM0 is connected to dw-apb-uart.0
com1_device
The serial ports (usually named COM1 within the BIOS) which provide access to the COMe
module serial port SER1_RX and SER1_TX.
Use the shell command 'dmesg | grep ttyS' to show which uart com port uses which ttyS device.
For Kontron boards SER1/COM1 is connected to dw-apb-uart.1
"""
COMe_module_settings = {
'COMe-bCL6': {
'gpio_base_addr' : 1016, # '$ cat /sys/class/gpio/gpiochip1016/label' should return gpio-kempld
'i2c_port' : 9,
'smbus_port' : 7,
'net_device' : 'eno1' # '$ ll /sys/class/net' should show which device is not virtual
'COMe-bCL6': { # board_name
'BCL6R113': { # bios_version
'gpiochip_label' : 'gpio-kempld',
'i2c_port' : 9,
'smbus_port' : 7,
'net_device' : 'eno1',
'com0_device' : '/dev/ttyS0',
'com1_device' : '/dev/ttyS1'
},
},
'COMe-bTL6': {
'gpio_base_addr' : 553, # '$ cat /sys/class/gpio/gpiochip553/label' should return gpio-kempld
'i2c_port' : 15,
'smbus_port' : 13,
'net_device' : 'enp35s0' # '$ ll /sys/class/net' should show which device is not virtual
'COMe-bTL6': { # board_name
'BTL6R110': { # bios_version
'gpiochip_label' : 'gpio-kempld',
'i2c_port' : 15,
'smbus_port' : 13,
'net_device' : 'enp35s0',
'com0_device' : '/dev/ttyS0',
'com1_device' : '/dev/ttyS1'
},
'BTL6R901': { # bios_version
'gpiochip_label' : 'gpio-kempld',
'i2c_port' : 15,
'smbus_port' : 13,
'net_device' : 'enp35s0',
'com0_device' : '/dev/ttyS1',
'com1_device' : '/dev/ttyS2'
}
}
}
......@@ -55,15 +140,24 @@ def COMe_module_attrib(attrib):
def COMe_module_name():
return COMe_module_attrib('board_name')
def COMe_module_gpio_base_addr():
return COMe_module_settings[COMe_module_name()]['gpio_base_addr']
def COMe_bios_version():
return COMe_module_attrib('bios_version')
def COMe_module_gpiochip_label():
return COMe_module_settings[COMe_module_name()][COMe_bios_version()]['gpiochip_label']
def COMe_module_i2c_port():
return COMe_module_settings[COMe_module_name()]['i2c_port']
return COMe_module_settings[COMe_module_name()][COMe_bios_version()]['i2c_port']
def COMe_module_smbus_port():
return COMe_module_settings[COMe_module_name()]['smbus_port']
return COMe_module_settings[COMe_module_name()][COMe_bios_version()]['smbus_port']
def COMe_module_net_device():
return COMe_module_settings[COMe_module_name()]['net_device']
return COMe_module_settings[COMe_module_name()][COMe_bios_version()]['net_device']
def COMe_module_com0_device():
return COMe_module_settings[COMe_module_name()][COMe_bios_version()]['com0_device']
def COMe_module_com1_device():
return COMe_module_settings[COMe_module_name()][COMe_bios_version()]['com1_device']
pts/test/pxiecome/python/test00.py
View file @ ec1d281d
......@@ -6,6 +6,12 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-11-14 INCAA Computers
# Changed board_name to product_name, board_version to product_version,
# board_serial to product_serial and board_asset_tag to product_sku
#------------------------------------------------------------------------
import sys
import time
......@@ -88,10 +94,10 @@ def main (default_directory='.'):
print "COMe Module used within the setup:"
print " Vendor: " + COMe_module_attrib('board_vendor')
print " Name: " + COMe_module_attrib('board_name')
print " Version: " + COMe_module_attrib('board_version')
print " Serial: " + COMe_module_attrib('board_serial')
print " Partnumber: " + COMe_module_attrib('board_asset_tag')
print " Name: " + COMe_module_attrib('product_name')
print " Version: " + COMe_module_attrib('product_version')
print " Serial: " + COMe_module_attrib('product_serial')
print " Partnumber: " + COMe_module_attrib('product_sku')
print " BIOS vendor: " + COMe_module_attrib('bios_vendor')
print " BIOS version: " + COMe_module_attrib('bios_version')
print " BIOS date: " + COMe_module_attrib('bios_date')
......
pts/test/pxiecome/python/test06.py
View file @ ec1d281d
......@@ -6,6 +6,12 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-11-14 INCAA Computers
# Added COM0_DEVICE to PXCT()
# Added VCOM_DEVICE to PXCT()
#------------------------------------------------------------------------
import sys
import time
......@@ -28,6 +34,8 @@ Check the serial communication of the front panel COM port (SER0) and the
serial interface to the FPGA (SER1).
"""
COM0_DEVICE = COMe_module_com0_device()
VCOM_DEVICE = '/dev/ttyUSB0'
def main (default_directory='.'):
......@@ -37,7 +45,7 @@ def main (default_directory='.'):
# Front panel COM port connected to the PXCT module in slot 2
print ""
com_PXCT_p = PXCT(device = '/dev/ttyS0')
com_PXCT_p = PXCT(device = COM0_DEVICE)
com_PXCT_p.connect()
response = com_PXCT_p.id()
print 'PXCT (SER0) ID response: %s' % (response),
......@@ -52,7 +60,7 @@ def main (default_directory='.'):
# Front panel USB4 port connected USB-Serial adapter and to the
# PXCT module in System Timing slot
print ""
com_PXCT_t = PXCT(device = '/dev/ttyUSB0')
com_PXCT_t = PXCT(device = VCOM_DEVICE)
com_PXCT_t.connect()
response = com_PXCT_t.id()
print 'PXCT (USB) ID response: %s' % (response),
......
pts/test/pxiecome/python/test07.py
View file @ ec1d281d
......@@ -6,6 +6,15 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-11-15 INCAA Computers
# Moved documentation to ptspxiecome.py
# 2022-12-15 INCAA Computers
# Removed GPIO_BASE_ADDR (base addr of the gpio is now set dynamically)
# Added GPIOCHIP_LABEL
# Added print of the used gpiochip
#------------------------------------------------------------------------
import sys
import time
......@@ -25,16 +34,9 @@ from PXIeCOMe_tFPGA import *
test07: Check GPIO
Check the COM Express GPI an GPO signals.
The GPIO is accessed using sysfs at /sys/class/gpio.
Within the /sys/class/gpio directory one or more files/links are present with
a filename like gpiochipXXX. Using the shell command 'll' or 'ls -l' the link
can be shown. The one using kempld-gpio should be used. The number XXX within
gpiochipXXX should be used as GPIO_BASE_ADDR.
Note: GPIO_BASE_ADDR is also used in other tests!
"""
GPIO_BASE_ADDR = COMe_module_gpio_base_addr()
GPIOCHIP_LABEL = COMe_module_gpiochip_label()
GPI0 = 0
GPI1 = 1
......@@ -70,11 +72,14 @@ def main (default_directory='.'):
ret_error = None
abort = None
come_gpio = COMe_GPIO(addr=GPIO_BASE_ADDR)
# GPIO
print ""
come_gpio = COMe_GPIO(label=GPIOCHIP_LABEL)
come_gpio.setup()
print 'Using GPIO %s via gpiochip%d' % (GPIOCHIP_LABEL, come_gpio.baseaddr())
print ""
# Internal serial port connected to the onboard FPGA
print ""
tFPGA = PXIeCOMe_tFPGA()
tFPGA.connect()
response = tFPGA.id()
......
pts/test/pxiecome/python/test08.py
View file @ ec1d281d
......@@ -6,6 +6,13 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-12-15 INCAA Computers
# Removed GPIO_BASE_ADDR (base addr of the gpio is now set dynamically)
# Added GPIOCHIP_LABEL
# Added print of the used gpiochip
#------------------------------------------------------------------------
import sys
import time
......@@ -68,7 +75,7 @@ COMe-bTL6 devices
I2C_ADAPTER = COMe_module_i2c_port()
SMBUS_ADAPTER = COMe_module_smbus_port()
GPIO_BASE_ADDR = COMe_module_gpio_base_addr()
GPIOCHIP_LABEL = COMe_module_gpiochip_label()
ADDR_I2C_MEM_KONTRON = 0x50
ADDR_I2C_MEM_PXIeCOMe = 0x54
......@@ -180,8 +187,12 @@ def main (default_directory='.'):
init_test_time = time.time()
ret_error = None
come_gpio = COMe_GPIO(addr=GPIO_BASE_ADDR)
# GPIO
print ""
come_gpio = COMe_GPIO(label=GPIOCHIP_LABEL)
come_gpio.setup()
print 'Using GPIO %s via gpiochip%d' % (GPIOCHIP_LABEL, come_gpio.baseaddr())
print ""
# I2C
print "Access Kontron ID memory at I2C 0x%02x" % (ADDR_I2C_MEM_KONTRON)
......
pts/test/pxiecome/python/test10.py
View file @ ec1d281d
......@@ -6,6 +6,12 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-11-15 INCAA Computers
# Added COM0_DEVICE to PXCT()
# Added VCOM_DEVICE to PXCT()
#------------------------------------------------------------------------
import sys
import time
......@@ -28,6 +34,9 @@ Check the interface to the PXI backplane using two PXCT modules and check the
PXI_TRIG[7:0], PXI_LBR6, PXI_GA[4:0] and PXI_STAR signals.
"""
COM0_DEVICE = COMe_module_com0_device()
VCOM_DEVICE = '/dev/ttyUSB0'
def pxi_init(com_tFPGA, com_PXCT):
# initialize all interface directions to input
com_tFPGA.set_pxi_trig_direction()
......@@ -279,7 +288,7 @@ def main (default_directory='.'):
# Front panel COM port connected to the PXCT module in slot 2
print ""
com_PXCT_p = PXCT(device = '/dev/ttyS0')
com_PXCT_p = PXCT(device = COM0_DEVICE)
com_PXCT_p.connect()
response = com_PXCT_p.id()
print 'PXCT (Peripheral) ID response: %s' % (response),
......@@ -319,7 +328,7 @@ def main (default_directory='.'):
# Front panel USB4 port connected USB-Serial adapter and to the
# PXCT module in System Timing slot
print ""
com_PXCT_t = PXCT(device = '/dev/ttyUSB0')
com_PXCT_t = PXCT(device = VCOM_DEVICE)
com_PXCT_t.connect()
response = com_PXCT_t.id()
print 'PXCT (System Timing) ID response: %s' % (response),
......
pts/test/pxiecome/python/test11.py
View file @ ec1d281d
......@@ -6,6 +6,15 @@
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
#------------------------------------------------------------------------
# Changes
# 2022-11-14 INCAA Computers
# Added COM0_DEVICE to PXCT()
# Changed trig_level_write_test tolerance from 50 to 70
# Changed trig_level_write_test tolerance from 25 to 35
# Changed trig_level_read_test tolerance from 50 to 70
# Changed trig_level_read_test tolerance from 25 to 35
#------------------------------------------------------------------------
import sys
import time
......@@ -27,6 +36,8 @@ test11: TRIG
Check the interface to the front panel TRIG port using one PXCT module.
"""
COM0_DEVICE = COMe_module_com0_device()
def trig_init(com_tFPGA, com_PXCT):
# initialize all interface directions to input
com_tFPGA.set_trig_direction()
......@@ -98,16 +109,16 @@ def trig_test(com_tFPGA, com_PXCT):
trig_level_write_test = [
{ 'write':0x0, 'level':40, 'tolerance':10, 'term':0},
{ 'write':0x1, 'level':2850, 'tolerance':50, 'term':0},
{ 'write':0x1, 'level':2850, 'tolerance':70, 'term':0},
{ 'write':0x0, 'level':15, 'tolerance':10, 'term':1},
{ 'write':0x1, 'level':1300, 'tolerance':25, 'term':1}
{ 'write':0x1, 'level':1300, 'tolerance':35, 'term':1}
]
trig_level_read_test = [
{ 'write':0x0, 'level':40, 'tolerance':10, 'term':0},
{ 'write':0x1, 'level':2850, 'tolerance':50, 'term':0},
{ 'write':0x1, 'level':2850, 'tolerance':70, 'term':0},
{ 'write':0x0, 'level':15, 'tolerance':10, 'term':1},
{ 'write':0x1, 'level':1300, 'tolerance':25, 'term':1}
{ 'write':0x1, 'level':1300, 'tolerance':35, 'term':1}
]
def trig_level_test(com_tFPGA, com_PXCT):
......@@ -157,7 +168,7 @@ def main (default_directory='.'):
# Front panel COM port connected to the PXCT module in slot 2
print ""
com_PXCT_p = PXCT(device = '/dev/ttyS0')
com_PXCT_p = PXCT(device = COM0_DEVICE)
com_PXCT_p.connect()
response = com_PXCT_p.id()
print 'PXCT (Peripheral Slot) ID response: %s' % (response),
......
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