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P
PXIe controller COM Express based testing support
Commit 6d536ce5 authored by Joseph Tagg's avatar Joseph Tagg
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version 1 of the PTS which adds support for the Kontron bTL6

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README.md
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# PTS for PXIe-COMe carrier
\ No newline at end of file
pts/LICENSE
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pts/README
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......@@ -3,5 +3,5 @@ This is Production Test Suite project.
Supporting automated hardware testing at BE/CO/HT
since 2011 or even less
License: GPL v2 or later
License: CERN-OHL-W-2.0+
pts/pxiecome.sh
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#!/bin/sh
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress
# designed by INCAA Computers
......
pts/test/pxiecome/python/COMe_GPIO.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
import sys
import os
import gpio
import subprocess
import logging
logging.getLogger("gpio").setLevel(logging.INFO)
......@@ -25,23 +25,84 @@ class COMe_GPIO(Item):
'gpi_offset':['GPI address offset', 'Offset GPI sysfs address', 0, int],
'gpo_offset':['GPO address offset', 'Offset GPO sysfs address', 4, int]}
IN, OUT = 'in', 'out'
def __init__(self, *args, **kwargs):
"""The initializer doesn't connect to the device."""
Item.__init__(self, *args, **kwargs)
self.gpo_base = self.addr + self.gpo_offset
self.gpi_base = self.addr + self.gpi_offset
def _shell(self, sysfs_cmd):
try:
df = subprocess.check_output(sysfs_cmd, shell=True, stderr=subprocess.STDOUT)
output = df.rstrip()
status = 0
except subprocess.CalledProcessError as e:
output = e.output.rstrip()
status = e.returncode
return output, status
def _unexport(self, chippin):
sysfs_cmd_unexport = "echo %d > /sys/class/gpio/unexport" % (chippin)
output, status = self._shell(sysfs_cmd_unexport)
if status != 0:
sysfs_cmd_export = "echo %d > /sys/class/gpio/export" % (chippin)
output, status = self._shell(sysfs_cmd_export)
if status == 0:
output, status = self._shell(sysfs_cmd_unexport)
return output
def _export(self, chippin):
sysfs_cmd_export = "echo %d > /sys/class/gpio/export" % (chippin)
output, status = self._shell(sysfs_cmd_export)
if status != 0:
sysfs_cmd_unexport = "echo %d > /sys/class/gpio/unexport" % (chippin)
output, status = self._shell(sysfs_cmd_export)
if status == 0:
output, status = self._shell(sysfs_cmd_export)
return output
def _set_direction(self, pin, direction):
sysfs_cmd = "echo %s > /sys/class/gpio/GPIO%d/direction" % (direction, pin)
self._shell(sysfs_cmd)
def _set_value(self, pin, value):
sysfs_cmd = "echo %d > /sys/class/gpio/GPIO%d/value" % (value, pin)
self._shell(sysfs_cmd)
def _get_value(self, pin):
sysfs_cmd = "cat /sys/class/gpio/GPIO%d/value" % (pin)
output, status = self._shell(sysfs_cmd)
return int(output)
def _setupGPI(self, pin):
if (pin < 0 | pin > 3):
return
gpi_chippin = int(pin) + self.gpi_base
gpi_pin = int(pin) + self.gpi_offset
self._export(gpi_chippin)
self._set_direction(gpi_pin, self.IN)
def _setupGPO(self, pin):
if (pin < 0 | pin > 3):
return
gpo_pin = int(pin) + self.gpo_base
gpio.setup(gpo_pin, gpio.OUT)
gpo_chippin = int(pin) + self.gpo_base
gpo_pin = int(pin) + self.gpo_offset
self._export(gpo_chippin)
self._set_direction(gpo_pin, self.OUT)
def _setupGPI(self, pin):
def _cleanupGPI(self, pin):
if (pin < 0 | pin > 3):
return
gpi_pin = int(pin) + self.gpi_base
gpio.setup(gpi_pin, gpio.IN)
gpi_chippin = int(pin) + self.gpi_base
self._unexport(gpi_chippin)
def _cleanupGPO(self, pin):
if (pin < 0 | pin > 3):
return
gpo_chippin = int(pin) + self.gpo_base
self._unexport(gpo_chippin)
def setup(self):
for i in range(0, 4):
......@@ -49,15 +110,17 @@ class COMe_GPIO(Item):
self._setupGPI(i)
def cleanup(self):
gpio.cleanup()
for i in range(0, 4):
self._cleanupGPO(i)
self._cleanupGPI(i)
def gpo(self, pin, value):
gpo_pin = int(pin) + self.gpo_base
gpio.set(gpo_pin, value)
gpio_pin = int(pin) + self.gpo_offset
self._set_value(gpio_pin, value)
def gpi(self, pin):
gpi_pin = int(pin) + self.gpi_base
return gpio.read(gpi_pin)
gpio_pin = int(pin) + self.gpi_offset
return int(self._get_value(gpio_pin))
if __name__ == "__main__":
main()
......
pts/test/pxiecome/python/COMe_Serial.py
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/python/PXCT.py
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/python/PXIeCOMe_tFPGA.py
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/python/ptspxiecome.py
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......@@ -13,9 +13,25 @@ import os
import subprocess
"""
PXIeCOMe PTS common functions
PXIeCOMe PTS common functions and settings
"""
COMe_module_settings = {
'COMe-bCL6': {
'gpio_base_addr' : 1016, # '$ cat /sys/class/gpio/gpiochip1016/label' should return gpio-kempld
'i2c_port' : 9,
'smbus_port' : 7,
'net_device' : 'eno1' # '$ ll /sys/class/net' should show which device is not virtual
},
'COMe-bTL6': {
'gpio_base_addr' : 553, # '$ cat /sys/class/gpio/gpiochip553/label' should return gpio-kempld
'i2c_port' : 15,
'smbus_port' : 13,
'net_device' : 'enp35s0' # '$ ll /sys/class/net' should show which device is not virtual
}
}
def shell_cat_file(f):
if os.path.exists(f):
sysfs_cmd = "cat " + f
......@@ -32,3 +48,22 @@ def print_error():
def print_ok():
print " [Ok]"
def COMe_module_attrib(attrib):
sysfs_file = '/sys/class/dmi/id/%s' % attrib
return shell_cat_file(sysfs_file)
def COMe_module_name():
return COMe_module_attrib('board_name')
def COMe_module_gpio_base_addr():
return COMe_module_settings[COMe_module_name()]['gpio_base_addr']
def COMe_module_i2c_port():
return COMe_module_settings[COMe_module_name()]['i2c_port']
def COMe_module_smbus_port():
return COMe_module_settings[COMe_module_name()]['smbus_port']
def COMe_module_net_device():
return COMe_module_settings[COMe_module_name()]['net_device']
pts/test/pxiecome/python/test00.py
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......@@ -85,6 +85,16 @@ def main (default_directory='.'):
ret_error = 'Incorrect setup.'
if abort:
raise PtsCritical(abort)
print "COMe Module used within the setup:"
print " Vendor: " + COMe_module_attrib('board_vendor')
print " Name: " + COMe_module_attrib('board_name')
print " Version: " + COMe_module_attrib('board_version')
print " Serial: " + COMe_module_attrib('board_serial')
print " Partnumber: " + COMe_module_attrib('board_asset_tag')
print " BIOS vendor: " + COMe_module_attrib('bios_vendor')
print " BIOS version: " + COMe_module_attrib('bios_version')
print " BIOS date: " + COMe_module_attrib('bios_date')
end_test_time = time.time()
print "End of Test00 (Setup)"
......
pts/test/pxiecome/python/test01.py
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/python/test02.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/python/test03.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......@@ -25,6 +25,8 @@ Check aspects of the LAN interface and perform a simple ping to a remote server.
This test also logs several LAN aspects and tests the LAN RJ45 LEDS
"""
NET_DEVICE = COMe_module_net_device()
def lan_check_ping():
hostname = "cern.org"
cmd = 'ping -c 1 %s' % (hostname)
......@@ -39,19 +41,19 @@ def lan_check_ping():
return status
def lan_operstate():
sysfs_file = '/sys/class/net/eno1/operstate'
sysfs_file = '/sys/class/net/%s/operstate' % (NET_DEVICE)
return shell_cat_file(sysfs_file)
def lan_speed():
sysfs_file = '/sys/class/net/eno1/speed'
sysfs_file = '/sys/class/net/%s/speed' % (NET_DEVICE)
return shell_cat_file(sysfs_file)
def lan_duplex():
sysfs_file = '/sys/class/net/eno1/duplex'
sysfs_file = '/sys/class/net/%s/duplex' % (NET_DEVICE)
return shell_cat_file(sysfs_file)
def lan_mac_address():
sysfs_file = '/sys/class/net/eno1/address'
sysfs_file = '/sys/class/net/%s/address' % (NET_DEVICE)
return shell_cat_file(sysfs_file)
tmp_stdout = sys.stdout
......
pts/test/pxiecome/python/test04.py
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......@@ -29,24 +29,24 @@ the D+/D- signal pair.
setup_image = [
"+-----------PXIeCOMe--------------+--PXCT--+",
"| LAN USB | | CHANGE PXIeCOMe interfaces:",
"| LAN USB | | Only CHANGE these interfaces:",
"| 10/100 +------+ +-+ +-+ | | ",
"| /1000 |o | | | | | o PWR | o | -USB6 to USB memory stick",
"| |o | |6| |5| o DRIVE | o STAT | -USB5 to USB memory stick",
"| ACT/ +------+ +-+ +-+ | | ",
"| LINK +-+ +-+ | | ",
"| | | | | USB | /--\ | -USB2 to mouse",
"| /--\ |4| |3| | | | | -USB1 to keyboard",
"| TRIG | | +-+ +-+ | \--/ | ",
"| \--/ +-+ +-+ | TRIG | ",
"| | | | | USB (SS)| | ",
"| +---\ |2| |1| | /---+ | ",
"| /1000 |o | | | | | o PWR | o | -USB6 to USB memory stick <-----",
"| |o | |6| |5| o DRIVE | o STAT | -USB5 to USB memory stick <-- |",
"| ACT/ +------+ +-+ +-+ | | | |",
"| LINK +-+ +-+ | | | |",
"| | | | | USB | /--\ | | |",
"| /--\ |4| |3| | | | | | |",
"| TRIG | | +-+ +-+ | \--/ | | |",
"| \--/ +-+ +-+ | TRIG | | |",
"| | | | | USB (SS)| | -USB2 to mouse <----------|---",
"| +---\ |2| |1| | /---+ | -USB1 to keyboard <-----------",
"| | | +-+ +-+ | | | | ",
"| COM | | +-+ | | | | ",
"| | | | | | | | | ",
"| +---/ | | DP | \---+ | ",
"| | | | COM | ",
"| +-/ | | ",
"| COM | | +-+ | | | | So swap the connections between",
"| | | | | | | | | USB1 and USB5, and",
"| +---/ | | DP | \---+ | USB2 and USB6",
"| | | | COM | And leave all other interfaces",
"| +-/ | | connected as they were.",
"+------------------------+-Slot 1-+-Slot 2-+"
]
......
pts/test/pxiecome/python/test05.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......@@ -26,7 +26,7 @@ temperature of the FPGA in addition to VCCINT and VCCAUX, and tests the DONE
and INIT LEDS.
"""
vivado_settings = "/home/incaa/Xilinx/Vivado_Lab/2021.1/settings64.sh"
vivado_settings = "/opt/Xilinx/Vivado_Lab/2021.1/settings64.sh"
pxct_image = [
"PXCT Board |",
......
pts/test/pxiecome/python/test06.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/python/test07.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......@@ -34,7 +34,7 @@ gpiochipXXX should be used as GPIO_BASE_ADDR.
Note: GPIO_BASE_ADDR is also used in other tests!
"""
GPIO_BASE_ADDR = 504
GPIO_BASE_ADDR = COMe_module_gpio_base_addr()
GPI0 = 0
GPI1 = 1
......@@ -169,8 +169,8 @@ def main (default_directory='.'):
stdio_redirect_start()
ask = "";
while ((ask != "Y") and (ask != "A")) :
print "-------------------------------------------------------------"
print "Please push the PROG button during the next 5 second."
print "--------------------------------------------------------------"
print "Please push the PROG button once during the next 5 second."
ask = raw_input("Ready to start the timer? [Y(es),A(bort)]")
ask = ask.upper()
print " "
......
pts/test/pxiecome/python/test08.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......@@ -25,49 +25,81 @@ from COMe_GPIO import *
test08: Check I2C and SMBus
Check the onboard I2C connection to the flash memory at 0x54.
And check the SMBus by reading the PXIe chassis ID eeprom at 0x52.
The used PXIe chassis is a NI PXIe-1075
And check the SMBus by reading the PXIe chassis ID eeprom at 0x52 or a device
at 0x2D.
The used PXIe chassis is a NI PXIe-1075, which has the backplane descriptor
eeprom at 0x52 and a backplane clocking CPLD at 0x2D
The I2C and SMBus interfaces are tested using one of the onboard i2c host
adapter devices. A list can be shown using the shell command 'i2cdetect -l'
For the I2C bus the host 'i2c-kempld' is used
For the SMBus the host 'SMiBus CMI adpater cmi' is used
On the Kontron COMe-bCL6 the SMBus is also used for the DDR SO-DIMM SPD flash
memory at 0x50 for slot 1 and at 0x52 for slot 2.
On the Kontron COMe-bCL6 and COMe-BTL6 the SMBus is also used for the DDR
SO-DIMM SPD flash memory at 0x50 for slot 1 and at 0x52 for slot 2.
The PXIe chassis ID eeprom is also at 0x52 and could result in a conflict.
But since SO-DIMM slot 2 is not used, the conflict doesn't occur.
This conflict is however prevented by the COMe-bCL6 BIOS through the
'SMBus I801 adapter' host adapter. So the 'SMiBus CMI adpater cmi' can only
be used.
Using SO-DIMM slot 2 will lead to a conflict and failure of the SMBus test!
When a SO-DIMM SPD flash memory is present at 0x52 the conflict prevents the
access to the backplane descriptor eeprom to test the SMBus. To overcome this
the test adjusts to use the SMBus device at 0x2D.
NI PXIe-1075 devices:
0x2D: backplane clocking CPLD
0x2E: temperature monitoring device
0x52: PXIe chassis ID eeprom / backplane descriptor eeprom
COMe-bCL6 devices
0x2E: hardware monitor NCT7802Y !!! Do not use under any circumstances !!!
0x50: SPD DDR Channel 1 (SO-DIMM)
0x52: SPD DDR Channel 2 (SO-DIMM)
0x18: SO-DIMM Thermal Sensor channel 1 (If available on the used memory-module)
0x1A: SO-DIMM Thermal Sensor channel 2 (If available on the used memory-module)
COMe-bTL6 devices
0x2E: hardware monitor NCT7802Y !!! Do not use under any circumstances !!!
0x50: DDR4 channel A EEPROM
0x52: DDR4 channel B EEPROM
0x53: DDR4 channel C EEPROM (optional)
"""
I2C_ADAPTER = 9 # i2c-9
SMBUS_ADAPTER = 7 # i2c-7
I2C_ADAPTER = COMe_module_i2c_port()
SMBUS_ADAPTER = COMe_module_smbus_port()
GPIO_BASE_ADDR = 504
GPIO_BASE_ADDR = COMe_module_gpio_base_addr()
ADDR_I2C_MEM_KONTRON = 0x50
ADDR_I2C_MEM_PXIeCOMe = 0x54
ADDR_SMBUS_MEM_PXIe = 0x52
ADDR_SMBUS_MEM_CHASSIS = 0x52 # NI PXIe-1075 Backplane Descriptor EEPROM
ADDR_SMBUS_DEV_CHASSIS = 0x2D # NI PXIe-1075 Backplane Clocking CPLD
def smbus_get(bus, address, reg):
# Use single access i2cget to overcome block read problems
cmd = 'i2cget -y %d 0x%02x %d' % (bus, address, reg)
try:
df = subprocess.check_output(cmd, shell=True, stderr=subprocess.STDOUT)
output = df.rstrip();
status = 0
except subprocess.CalledProcessError as e:
output = e.output.rstrip()
status = e.returncode
if (status == 0):
value = int(output, base=16)
else:
value = 0
return value, status, output
def smbus_dump(bus, address):
# Use single access i2cget to overcome block read problems
dump = []
for reg in range(0, 256):
cmd = 'i2cget -y %d 0x%02x %d' % (bus, address, reg)
try:
df = subprocess.check_output(cmd, shell=True, stderr=subprocess.STDOUT)
output = df.rstrip();
status = 0
except subprocess.CalledProcessError as e:
output = e.output.rstrip()
status = e.returncode
break
value, status, output = smbus_get(bus, address, reg)
if (status == 0):
value = int(output, base=16)
dump.append(value)
dump.append(value)
else:
break
return dump, status, output
def i2c_dump(bus, address):
......@@ -166,47 +198,68 @@ def main (default_directory='.'):
print_error()
print ""
print "Access PXIeCOMe ID memory at I2C 0x%02x" % (ADDR_I2C_MEM_PXIeCOMe)
print "Access PXIeCOMe memory at I2C 0x%02x" % (ADDR_I2C_MEM_PXIeCOMe)
dump, status, output = i2c_dump(I2C_ADAPTER, ADDR_I2C_MEM_PXIeCOMe)
if status == 0:
print_hex(dump)
print_ok()
else:
ret_error = "PXIeCOMe ID memory access error %d: %s" % (status, output)
ret_error = "PXIeCOMe memory access error %d: %s" % (status, output)
print_error()
print ""
# SMBus
come_gpio.gpo(3, 0)
print "Access PXIe ID memory at SMBus 0x%02x (should not exist)" % (ADDR_SMBUS_MEM_PXIe)
dump, status, output = smbus_dump(SMBUS_ADAPTER, ADDR_SMBUS_MEM_PXIe)
checkSMBusMem = True
print "Check access to memory at SMBus 0x%02x." % (ADDR_SMBUS_MEM_CHASSIS)
dump, status, output = smbus_dump(SMBUS_ADAPTER, ADDR_SMBUS_MEM_CHASSIS)
if status == 0:
print_hex(dump)
ret_error = "Memory found at 0x%02x. Probably conflict with onboard device." % (ADDR_SMBUS_MEM_PXIe)
print_error()
print "Memory found at 0x%02x. Probably conflict with %s device." % (ADDR_SMBUS_MEM_CHASSIS, COMe_module_name())
print ""
checkSMBusMem = False
print "Check access to device at SMBus 0x%02x" % (ADDR_SMBUS_DEV_CHASSIS)
value, status, output = smbus_get(SMBUS_ADAPTER, ADDR_SMBUS_DEV_CHASSIS, 0x00)
if status == 0:
print output
ret_error = "Device found at 0x%02x. Probably conflict with %s device." % (ADDR_SMBUS_DEV_CHASSIS, COMe_module_name())
print_error()
else:
if status == 2: # Read failed
print "No device found at 0x%02x [OK]" % (ADDR_SMBUS_DEV_CHASSIS)
else:
ret_error = "SMBus device access error %d: %s." % (status, output)
print_error()
else:
if status == 2: # Read failed
print "No memory found at 0x%02x [OK]" % (ADDR_SMBUS_MEM_PXIe)
print "No memory found at 0x%02x [OK]" % (ADDR_SMBUS_MEM_CHASSIS)
else:
ret_error = "PXIe ID memory access error %d: %s" % (status, output)
ret_error = "SMBus memory access error %d: %s." % (status, output)
print_error()
print ""
print "Enable SMBus access to chassis/backplane."
come_gpio.gpo(3, 1)
print "Access PXIe ID memory at SMBus 0x%02x (should exist)" % (ADDR_SMBUS_MEM_PXIe)
dump, status, output = smbus_dump(SMBUS_ADAPTER, ADDR_SMBUS_MEM_PXIe)
if status == 0:
print_hex(dump)
if find_str_in_list(dump, "PXIe-1075") < 0:
ret_error = "PXIe-1075 ID memory not found"
print_error()
else:
print ""
if checkSMBusMem:
print "Check access to memory at SMBus 0x%02x (should exist)." % (ADDR_SMBUS_MEM_CHASSIS)
dump, status, output = smbus_dump(SMBUS_ADAPTER, ADDR_SMBUS_MEM_CHASSIS)
if status == 0:
print_hex(dump)
print_ok()
else:
ret_error = "SMBus memory access error %d: %s." % (status, output)
print_error()
else:
ret_error = "PXIe ID memory access error %d: %s" % (status, output)
print_error()
print "Check access to device at SMBus 0x%02x (should exist)." % (ADDR_SMBUS_DEV_CHASSIS)
value, status, output = smbus_get(SMBUS_ADAPTER, ADDR_SMBUS_DEV_CHASSIS, 0x00)
if status == 0:
print_ok()
else:
ret_error = "SMBus device access error %d: %s." % (status, output)
print_error()
print ""
come_gpio.gpo(3, 0)
......
pts/test/pxiecome/python/test09.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......@@ -34,10 +34,23 @@ def pci_link_exist(bus, slot=0, func=0):
sysfs_file = '/sys/bus/pci/devices/%04x:%02x:%02x.%01x' % (domain, bus, slot, func)
return os.path.exists(sysfs_file)
def pci_link_can_wakeup(bus, slot=0, func=0):
def pci_link_is_upstream_port(bus, slot=0, func=0):
domain = 0
sysfs_file = '/sys/bus/pci/devices/%04x:%02x:%02x.%01x/wakeup' % (domain, bus, slot, func)
return os.path.exists(sysfs_file)
cmd = "lspci -s %x:%x:%x.%x -v" % (domain, bus, slot, func)
try:
df = subprocess.check_output(cmd, shell=True, stderr=subprocess.STDOUT)
output = df.rstrip()
status = 0
except subprocess.CalledProcessError as e:
output = e.output.rstrip()
status = e.returncode
if status == 0:
loc = output.find("Upstream Port")
if loc == -1:
return False
else:
return True
return False
def pci_link_attrib(file, bus, slot=0, func=0):
domain = 0
......@@ -60,7 +73,9 @@ def pci_link_speed(bus, slot=0, func=0):
speed = pci_link_attrib("current_link_speed", bus, slot, func)
if speed == "None":
speed = "0 GT/s"
speed = speed[:len(speed)-4]
loc = speed.find("GT/s")
speed = speed[:loc]
#speed = speed[:len(speed)-6]
return float(speed)
def pci_link_width(bus, slot=0, func=0):
......@@ -80,9 +95,9 @@ def main (default_directory='.'):
for bus in range(0x00, 0x20):
for slot in range(0x00, 0x20):
if pci_link_exist(bus, slot):
if pci_link_can_wakeup(bus, slot):
if (pci_link_has_vendor_and_device("0x10b5" , "0x8525", bus, slot) or
if (pci_link_has_vendor_and_device("0x10b5" , "0x8525", bus, slot) or
pci_link_has_vendor_and_device("0x10b5", "0x8533", bus, slot)):
if pci_link_is_upstream_port(bus, slot):
speed = pci_link_speed(bus, slot)
width = pci_link_width(bus, slot)
print "PCIe(%02x:%02x) speed %2.1f GT/s, width %d, id %s:%s" % (
......
pts/test/pxiecome/python/test10.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/python/test11.py
View file @ 6d536ce5
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/tcl/vivado_boot_device.tcl
View file @ 6d536ce5
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/tcl/vivado_temperature.tcl
View file @ 6d536ce5
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/tcl/vivado_vccaux.tcl
View file @ 6d536ce5
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
pts/test/pxiecome/tcl/vivado_vccint.tcl
View file @ 6d536ce5
# Copyright CERN, 2021
# Copyright CERN, 2021-2022
# This source describes Open Hardware and is licensed under the
# CERN-OHL-S v2
# CERN-OHL-W-2.0+
# Source location: https://ohwr.org/project/pxie-ctl-comexpress-tst
# designed by INCAA Computers
......
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