# Author: Richard Carrillo <rcarrillo(AT)sevensols.com>
# Author: Rafael Rodríguez <rrodriguez(AT)sevensols.com>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Website: http://www.sevensols.com
# Version: 1.0 (Last modifications: 21/12/2012)
# Version: 1.1 (Last modifications: 17/01/2013)
# remove unused libraries?
importsys
importrr
importrandom
importtime
importspi
importi2c
importgn4124
importos
importmath
fromptsexceptimport*
...
...
@@ -27,8 +25,8 @@ User intervention required: No
Procedure details:
- Load FPGA firmware
- Set local bus frequency
- Test the connectivity of address lines
- Test the connectivity of data lines
- Test the connectivity of address lines
"""
classtest07:
...
...
@@ -91,6 +89,10 @@ class test07:
break
returnret_error
deffind_different_bit(self,dword0,dword1):
""" Return the number of the most significant bit which is different in the two values """
returnint(math.floor(math.log(dword0^dword1,2)))
deftest_data_lines(self):
""" Test the memory-interface data lines """
ret_error=None
...
...
@@ -106,7 +108,7 @@ class test07:
self.gennum.wait_irq()
page_data=self.gennum.get_memory_page(0)
ifpage_data[0]<>value_list[data_line]:
error_str="Value read from memory (0x{:X}) is differnt from what was expected (0x{:X}) at Wishbone address (0x{:X}). DDR-interface data line/s is tied to Vcc or GND, or unconnected.".format(page_data[0],value_list[data_line],test_data_addr)
error_str="Value read from memory (0x{:X}) is differnt from what was expected (0x{:X}) at Wishbone address (0x{:X}). At least DDR-interface data line {} is tied to Vcc or GND, or unconnected.".format(page_data[0],value_list[data_line],test_data_addr,self.find_different_bit(page_data[0],value_list[data_line]))
print(error_str)
ret_error="While testing DDR data lines: "+error_str