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Production Test Suite - base
Commit e1613c48 authored by Matthieu Cattin's avatar Matthieu Cattin
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common: remove useless import (rawrabbit library).

parent f23a9beb
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Showing with 4 additions and 10 deletions
common/csr.py
View file @ e1613c48
...@@ -11,7 +11,7 @@ import sys ...@@ -11,7 +11,7 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
# Class to access 32-bit wishbone registers on BAR0 # Class to access 32-bit wishbone registers on BAR0
......
common/ds18b20.py
View file @ e1613c48
...@@ -13,7 +13,6 @@ import sys ...@@ -13,7 +13,6 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
from onewire import * from onewire import *
# Class to access the DS18B20 (temperature sensor & unique ID) chip. # Class to access the DS18B20 (temperature sensor & unique ID) chip.
......
common/eeprom_24aa64.py
View file @ e1613c48
...@@ -13,7 +13,6 @@ import sys ...@@ -13,7 +13,6 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
from i2c import * from i2c import *
# Class to access the 24AA64 (64K EEPROM) chip. # Class to access the 24AA64 (64K EEPROM) chip.
......
common/gn4124.py
View file @ e1613c48
...@@ -12,7 +12,6 @@ import sys ...@@ -12,7 +12,6 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
import csr import csr
# Class to access the GN4124 (PCIe bridge) chip. # Class to access the GN4124 (PCIe bridge) chip.
......
common/i2c.py
View file @ e1613c48
...@@ -13,7 +13,7 @@ import sys ...@@ -13,7 +13,7 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
# Class to access the wishbone to I2C master module from OpenCores # Class to access the wishbone to I2C master module from OpenCores
# http://opencores.org/project,i2c # http://opencores.org/project,i2c
......
common/ltc217x.py
View file @ e1613c48
...@@ -12,7 +12,6 @@ import sys ...@@ -12,7 +12,6 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
from spi import * from spi import *
# Class to access the LTC217x (ADC) chip. # Class to access the LTC217x (ADC) chip.
......
common/max5442.py
View file @ e1613c48
...@@ -12,7 +12,6 @@ import sys ...@@ -12,7 +12,6 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
from spi import * from spi import *
# Class to access the MAX5442 (DAC) chip. # Class to access the MAX5442 (DAC) chip.
......
common/onewire.py
View file @ e1613c48
...@@ -13,7 +13,7 @@ import sys ...@@ -13,7 +13,7 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
# Class to access the wishbone to onewire master module from OpenCores # Class to access the wishbone to onewire master module from OpenCores
# http://opencores.org/project,sockit_owm # http://opencores.org/project,sockit_owm
......
common/si57x.py
View file @ e1613c48
...@@ -12,7 +12,6 @@ import sys ...@@ -12,7 +12,6 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
from i2c import * from i2c import *
# Class to access the Si57x (VCXO) chip. # Class to access the Si57x (VCXO) chip.
......
common/spi.py
View file @ e1613c48
...@@ -12,7 +12,7 @@ import sys ...@@ -12,7 +12,7 @@ import sys
import time import time
# Import specific modules # Import specific modules
import rr
# Class to access the wishbone to SPI master module from OpenCores # Class to access the wishbone to SPI master module from OpenCores
# http://opencores.org/project,spi # http://opencores.org/project,spi
......
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