Commit e1613c48 authored by Matthieu Cattin's avatar Matthieu Cattin

common: remove useless import (rawrabbit library).

parent f23a9beb
......@@ -11,7 +11,7 @@ import sys
import time
# Import specific modules
import rr
# Class to access 32-bit wishbone registers on BAR0
......
......@@ -13,7 +13,6 @@ import sys
import time
# Import specific modules
import rr
from onewire import *
# Class to access the DS18B20 (temperature sensor & unique ID) chip.
......
......@@ -13,7 +13,6 @@ import sys
import time
# Import specific modules
import rr
from i2c import *
# Class to access the 24AA64 (64K EEPROM) chip.
......
......@@ -12,7 +12,6 @@ import sys
import time
# Import specific modules
import rr
import csr
# Class to access the GN4124 (PCIe bridge) chip.
......
......@@ -13,7 +13,7 @@ import sys
import time
# Import specific modules
import rr
# Class to access the wishbone to I2C master module from OpenCores
# http://opencores.org/project,i2c
......
......@@ -12,7 +12,6 @@ import sys
import time
# Import specific modules
import rr
from spi import *
# Class to access the LTC217x (ADC) chip.
......
......@@ -12,7 +12,6 @@ import sys
import time
# Import specific modules
import rr
from spi import *
# Class to access the MAX5442 (DAC) chip.
......
......@@ -13,7 +13,7 @@ import sys
import time
# Import specific modules
import rr
# Class to access the wishbone to onewire master module from OpenCores
# http://opencores.org/project,sockit_owm
......
......@@ -12,7 +12,6 @@ import sys
import time
# Import specific modules
import rr
from i2c import *
# Class to access the Si57x (VCXO) chip.
......
......@@ -12,7 +12,7 @@ import sys
import time
# Import specific modules
import rr
# Class to access the wishbone to SPI master module from OpenCores
# http://opencores.org/project,spi
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment