Review25032010
Design review of NanoFIP Test Board
25 March 2010
Schematics of 19 March 2010. Schematics and other documentation of the
verified version at link
Present
Matthieu Cattin (BE/CO), Pablo Alvarez (BE/CO), Erik van der Bij (BE/CO)
General description of the design.
The company HLP has written specifications and made the schematics for the NanoFIP test board. This review verified the documentation and notably the schematics before the PCB layout will start at HLP.
Detailed comments on schematics
Conclusions
This has been a very useful review that revealed several serious mistakes and signalled other issues that will make the design more robust and that will improve its documentation. The changes will be implemented before finalising the PCB layout. We thank all people involved in the review.
- Erik van der Bij - 25 March 2010